mirror of https://github.com/openXC7/prjxray.git
101-dsp-pips: solve DSP-related PIPs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
953f8745ba
commit
8266247637
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@ -0,0 +1,61 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=dsp
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PIPLIST_TCL=$(FUZDIR)/dsp_pip_list.tcl
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BUILD_DIR = build
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RUN_OK = run.ok
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TODO_RE=".*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "l,r"
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N = 1
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SEGMATCH_FLAGS=-c 1
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A_PIPLIST=dsp_l.txt
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CHECK_ARGS= --zero-entries --timeout-iters 2
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include ../pip_loop.mk
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$(BUILD_DIR)/segbits_dsp_l.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_dsp_l.rdb \
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$(shell find $(BUILD_DIR) -name segdata_dsp_l.txt)
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$(BUILD_DIR)/segbits_dsp_r.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_dsp_r.rdb \
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$(shell find $(BUILD_DIR) -name segdata_dsp_r.txt)
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RDBS = $(BUILD_DIR)/segbits_dsp_l.rdb $(BUILD_DIR)/segbits_dsp_r.rdb
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_dsp_l.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_dsp_l.db
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_dsp_r.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_dsp_r.db
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# Keep a copy to track iter progress
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cp $(BUILD_DIR)/segbits_dsp_l.rdb $(BUILD_DIR)/$(ITER)/segbits_dsp_l.rdb
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cp $(BUILD_DIR)/segbits_dsp_l.db $(BUILD_DIR)/$(ITER)/segbits_dsp_l.db
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cp $(BUILD_DIR)/segbits_dsp_r.rdb $(BUILD_DIR)/$(ITER)/segbits_dsp_r.rdb
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cp $(BUILD_DIR)/segbits_dsp_r.db $(BUILD_DIR)/$(ITER)/segbits_dsp_r.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} dsp_l $(BUILD_DIR)/segbits_dsp_l.db
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} dsp_r $(BUILD_DIR)/segbits_dsp_r.db
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pushdb: database
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${XRAY_MERGEDB} dsp_l $(BUILD_DIR)/segbits_dsp_l.db
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${XRAY_MERGEDB} dsp_r $(BUILD_DIR)/segbits_dsp_r.db
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.PHONY: database pushdb run clean
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@ -0,0 +1,45 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] {
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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# Skip pips with disconnected nodes
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set src_node [get_nodes -of_objects $src]
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if { $src_node == {} || !([regexp "VCC" $src_node] || [regexp "GND" $src_node]) } {
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continue
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}
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set dst_node [get_nodes -of_objects $dst]
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if { $dst_node == {} } {
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continue
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}
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if { [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1 } {
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set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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dict set pips $pip_string 1
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}
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}
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips DSP_R dsp_r.txt
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print_tile_pips DSP_L dsp_l.txt
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@ -0,0 +1,98 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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if frame not in [26, 27]:
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return False
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return True
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def read_pip_data(pipfile, pipdata, tile_ports):
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'dsp', pipfile)) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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read_pip_data('dsp_r.txt', pipdata, tile_ports)
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read_pip_data('dsp_l.txt', pipdata, tile_ports)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('DSP'):
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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else:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,35 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-1}]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-3}]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-5}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-21}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-25}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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route_design -directive Quick
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,25 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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ports = {
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"DSP48E1": [
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("ALUMODE", 4),
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("CARRYINSEL", 3),
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("CEAD", 1),
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("CEALUMODE", 1),
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("CED", 1),
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("CEINMODE", 1),
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("D", 25),
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("INMODE", 5),
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("OPMODE", 7),
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("RSTD", 1),
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],
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}
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@ -0,0 +1,95 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os
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import random
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import math
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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from ports import ports
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def print_site(ports, luts, site, site_type):
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verilog_ports = ""
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verilog_wires = ""
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for port, width in ports:
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verilog_ports += """
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.{port}({port}_{site}),""".format(
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port=port, site=site)
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verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site)
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for idx in range(0, width):
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rand = random.random()
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if rand < 0.45:
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source = "1'b0"
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elif rand < 0.9:
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source = "1'b1"
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else:
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source = luts.get_next_output_net()
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verilog_wires += "assign {}_{}[{}] = {};\n".format(
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port, site, idx, source)
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verilog_wires += "\n"
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verilog_ports = verilog_ports.rstrip(",")
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print(
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"""
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{wires}
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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{site_type} #(.AREG(2), .BREG(2)) {site}_instance (
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{ports}
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);""".format(
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wires=verilog_wires,
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ports=verilog_ports,
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site=site,
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site_type=site_type))
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def main():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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luts = LutMaker()
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def gen_sites(desired_site_type):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield tile_name, site
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print('''
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module top();
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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''')
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for site_type in ["DSP48E1"]:
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for _, site in gen_sites(site_type):
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print_site(ports[site_type], luts, site, site_type)
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for l in luts.create_wires_and_luts():
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print(l)
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print('endmodule')
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if __name__ == "__main__":
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main()
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@ -168,6 +168,7 @@ endif
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endif
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endif
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$(eval $(call fuzzer,100-dsp-mskpat,005-tilegrid,all))
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$(eval $(call fuzzer,101-dsp-pips,005-tilegrid,all))
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quick:
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$(MAKE) QUICK=Y
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