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prjxray/minitests/srl
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Maciej Kurc 5c60639442 Added generation of sorted and "uniqued" FASM output 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2019-07-05 12:03:30 +02:00
..
Makefile Added generation of sorted and "uniqued" FASM output 2019-07-05 12:03:30 +02:00
README.md Added minitests for SRLs 2019-06-27 15:13:18 +02:00
par.tcl Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_init.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x1.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x1_and_lut6_x3.v Added packing tests for SRL32+LUT6 2019-06-28 10:53:27 +02:00
srl32_x2.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x2_and_lut6_x2.v Added packing tests for SRL32+LUT6 2019-06-28 10:53:27 +02:00
srl32_x2_chain.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x3.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x3_and_lut6_x1.v Added packing tests for SRL32+LUT6 2019-06-28 10:53:27 +02:00
srl32_x3_chain.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x4.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
srl32_x4_chain.v Added minitests for SRLs 2019-06-27 15:13:18 +02:00
syn.tcl Added full vivado flow to the Makefile 2019-06-28 10:53:22 +02:00

README.md

Minitests for SRLs

This is a minitest for various SRL configurations.

Uses Yosys to generate EDIF which is then P&R'd by Vivado. The makefile also invokes bit2fasm and segprint