0e3f20b577
propagate_IOB_SING and propagate_IOI_SING set the top SING-row tile's alias start_offset to 0, mapping the full tile's lower words (0-1) into the tile's only frame words (99-100). But nextpnr-xilinx targets the full tile's UPPER OLOGIC/IOB words (2-3) on the top SING tile; under start_offset 0 those map to absolute frame words 101-102, which don't exist, so fasm2frames raises "invalid word address" and silently drops the features (e.g. a VC707 LED or UART output on LIOI_SING_X82Y51.OLOGIC_Y0). start_offset 2 (effective offset 97) lands words 2-3 at abs 99-100 -- matching the bottom SING tiles and the HW-verified tilegrid data fix. Confirmed by re-running fuzzer 036-iob18-ologic-sing (OLOGIC_Y0.OMUX.D1 at abs word 100) and by the open-flow UART DSP calculator computing correctly on hardware. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> |
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|---|---|---|
| .. | ||
| bram | ||
| bram_block | ||
| bram_int | ||
| cfg | ||
| cfg_int | ||
| clb | ||
| clb_int | ||
| clk_bufg | ||
| clk_hrow | ||
| dsp | ||
| dsp_int | ||
| fifo_int | ||
| fuzzaddr | ||
| gtp_channel | ||
| gtp_common | ||
| gtp_int_interface | ||
| gtx_channel | ||
| gtx_common | ||
| gtx_int_interface | ||
| hclk_cmt | ||
| hclk_ioi | ||
| iob | ||
| iob18 | ||
| iob18_int | ||
| iob18_sing | ||
| iob_int | ||
| ioi | ||
| ioi18 | ||
| mmcm | ||
| monitor | ||
| monitor_int | ||
| orphan_int_column | ||
| pcie | ||
| pcie_int_interface | ||
| pll | ||
| ps7_int | ||
| Makefile | ||
| README.md | ||
| add_tdb.py | ||
| generate.py | ||
| generate.sh | ||
| generate_full.py | ||
| generate_tiles.tcl | ||
| top.v | ||
| util.py | ||
| util.tcl | ||
README.md
Tilegrid Fuzzer
This fuzzer creates the tilegrid.json bitstream database. This database contains segment definitions including base frame address and frame offsets.
Example workflow for CLB
generate.tcl LOCs one LUT per segment column towards generating frame base addresses.
A reference bitstream is generated and then:
- a series of bitstreams are generated each with one LUT bit toggled; then
- these are compared to find a toggled bit in the CLB segment column; then
- the resulting address is truncated to get the base frame address.
Finally, generate.py calculates the segment word offsets based on known segment column structure
Environment variables
XRAY_ROI
This environment variable must be set with a valid ROI. See database for example values
XRAY_EXCLUDE_ROI_TILEGRID
This environment variable must be set in case the part selected does not allow some tiles to be locked.
Error example (when using the artix 200T part):
ERROR: [Place 30-25] Component carry4_SLICE_X82Y249 has been locked to a prohibited site SLICE_X82Y249.
To avoid this error, the XRAY_EXCLUDE_ROI_TILEGRID defines an ROI that is not taken into account
when building the tilegrid, therefore excluding the problematic un-lockable sites.
As the resulting output file, tilegrid.json, is going to be checked against the one produced in
the 074-dump_all fuzzer, also the latter one needs to produce a reduced tilegrid, with the excluded
tiles specified with the environment variable.
XRAY_ROI_FRAMES
This can be set to a specific value to speed up processing and reduce disk space If you don't know where your ROI is, just set to to include all values (0x00000000:0xfffffff)
XRAY_ROI_GRID_*
Optionally, use these as a small performance optimization:
- XRAY_ROI_GRID_X1
- XRAY_ROI_GRID_X2
- XRAY_ROI_GRID_Y1
- XRAY_ROI_GRID_Y2
These should, if unused, be set to -1, with this caveat:
WARNING: CLB test generates this based on CLBs but implicitly includes INT
Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail if you don't have a CLB*_L at left and a CLB*_R at right.