prjxray/minitests/litex/src.vivado
litghost c94cb0224c
Revert "Whitespace"
2019-10-23 14:22:17 -07:00
..
Makefile Added source files dependencies to Makefiles 2019-06-25 10:14:20 +02:00
VexRiscv_Linux.v Revert "Whitespace" 2019-10-23 14:22:17 -07:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
top.tcl Added bitread and segprint to the Makefile flow 2019-06-17 14:52:06 +02:00
top.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00