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1494 Commits

Author SHA1 Message Date
John McMaster b8ced4e5ae
Merge pull request #487 from antmicro/456_regression_on_CLB_bit 
Bug #456: fix regression in CLB bit CARRY4.ACY0
 2019-01-11 08:23:16 +01:00
Tomasz Michalak 144a0edc8c Bug #456: fix regression in CLB bit CARRY4.ACY0 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-01-11 08:13:54 +01:00
Tim Ansell 7eb7d844b1
Merge pull request #491 from mithro/tests 
Making tests run on travis
 2019-01-11 06:08:16 +01:00
Tim 'mithro' Ansell f5b343fcf6 htmlgen: Fix escape sequence. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 20:10:52 -08:00
Tim 'mithro' Ansell 463000bafd infra: Refactor travis. 
* Use build stages to be clearer.
 * Run Python / C++ tests / Format separately.
 * Reduce duplication

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 20:07:08 -08:00
Tim 'mithro' Ansell 0def5b2eeb infra: Add docs to make format. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 19:56:33 -08:00
Tim 'mithro' Ansell 22fe886d44 Make Python code testable. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 19:54:59 -08:00
Tim 'mithro' Ansell 96c1874131 infra: Make travis run tests 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 19:54:53 -08:00
Tim 'mithro' Ansell 136d367f99 Refactor Makefile. 
* Split up file better.
 * Add test running.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 18:48:59 -08:00
Tim 'mithro' Ansell 841905c1e0 Adding `make test` target. 
Uses [py.test](https://pytest.org) to collect all Python doctests and
unittests.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 18:48:48 -08:00
Tim 'mithro' Ansell 9ebaf01de6 Add fasm into the environment. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 18:48:48 -08:00
Tim 'mithro' Ansell 88e68414bf Move .update-contributing.py script under .github directory. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-01-10 18:48:48 -08:00
John McMaster 517abfdc36
Merge pull request #486 from mcmasterg/timing_readme 
timfuz: update readme
 2019-01-10 16:05:53 +01:00
John McMaster 9fdd4fab86 timfuz: update readme 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-10 16:01:04 +01:00
John McMaster dff1402dfa
Merge pull request #474 from antmicro/05x-fuzzers-rework 
05x fuzzers rework
 2019-01-10 15:03:00 +01:00
Karol Gugala 6c6e90db84 fuzzers: 05x: do not use symbolic link to int_generate.py 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-10 14:36:36 +01:00
Karol Gugala 42529b7287 fuzzers: 51: calculate 50 DB entries in each step 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-10 12:46:41 +01:00
John Mcmaster eae584d5a5
Merge pull request #482 from antmicro/add-tdb-fixme 
005-tilegrid/add_tdb.py: added frame check
 2019-01-10 12:37:06 +01:00
Alessandro Comodi 65f5ddb030 005-tilegrid/add_tdb.py: use floor divide 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 12:04:34 +01:00
Alessandro Comodi b4ca31cd1e 005-tilegrid/add_tdb.py: added frame check 
This solves issue #481. add_tdb.py now checks if all the bits in a same
tag have the same base address and, if that is the case, the first of
them is selected

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 11:43:53 +01:00
John McMaster 08aaa19551
Merge pull request #462 from antmicro/ps7 
PS7 INT on Zynq
 2019-01-10 10:47:42 +01:00
Alessandro Comodi 3738801ca3 005-tilegrid: removing unneeded comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 10:22:36 +01:00
Alessandro Comodi 39693b7958 ps7_int: rename fuzzer ps7 --> ps7_int 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 10:02:08 +01:00
Alessandro Comodi bd32e51a38 005-tilegrid/add_tdb.py: change ps7 --> ps7_int 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 10:01:32 +01:00
Alessandro Comodi f8b5de960c ps7_int/Makefile: change ps7 --> ps7_int 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-10 10:00:49 +01:00
John McMaster e9a2489c36
Merge pull request #478 from litghost/add_ppips_for_bram 
Add ppips for bram
 2019-01-10 09:32:02 +01:00
John McMaster 35f6d83e77
Merge pull request #479 from mcmasterg/bram_dox_reg 
bram config: DOX_REG, clean up
 2019-01-10 09:31:04 +01:00
John McMaster 81fbb37153 bram config: DOX_REG, clean up 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-10 08:44:51 +01:00
Keith Rothman 150795d6d3 Add BRAM_INT_INTERFACE_* too. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-01-09 18:04:20 -08:00
Keith Rothman 55201c4d1e Add ppip output for BRAM tiles. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-01-09 17:10:01 -08:00
John McMaster 5079cbb383
Merge pull request #475 from mcmasterg/multi 
tilegrid: fix "multi" regression
 2019-01-10 00:08:34 +01:00
John McMaster bba4f339cc tilegrid: fix multi regression 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-09 23:29:21 +01:00
John McMaster f93c16c9bb
Merge pull request #473 from litghost/fix_circular_dependency 
Remove circular import dependency.
 2019-01-09 23:22:28 +01:00
Karol Gugala a4b0c6f1de fuzzers: refactor fuzzer 51 
The fuzzer is now todo files based. It is also using generic
generate.py script.
For now the fuzzer instantiates picorv and randluts besides
the logic under test. This is required for to deliver negative
examples to segmaker. Because of the size of the design this
fuzzer is taking really long to complete. We need to find a
smallest possible design that will be enough to generate the DB.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 23:16:22 +01:00
Karol Gugala e6eb0db9f9 utils: top_generate: generate setseed.vh for all targets 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 23:16:22 +01:00
Karol Gugala 49d8a6c22c fuzzers: 56: use generic generate.py 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 23:16:22 +01:00
Karol Gugala 5ea696b632 utils: pass flages to generate.py 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 23:16:22 +01:00
Karol Gugala bc48baa30d fuzzers: add generic generate.py 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 23:16:19 +01:00
Keith Rothman 5c980cace7 Remove circular import dependency. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-01-09 13:14:30 -08:00
Karol Gugala eb11da50e0 fuzzers: int_loop: do not mask errors 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-01-09 22:12:47 +01:00
Alessandro Comodi 7f6e6f1c8c 005-tilegrid/add_tdb.py: Changed frame and word params 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-09 19:07:40 +01:00
John McMaster e98c808443
Merge pull request #471 from mcmasterg/fuzaddr_optional 
fuzzaddr: optional dframe, dbit
 2019-01-09 19:05:21 +01:00
Alessandro Comodi 3ec9dd58af Merge branch 'master' into ps7 2019-01-09 18:52:28 +01:00
John McMaster 892b4fb5f7 fuzzaddr: optional dframe, dbit 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-09 18:45:37 +01:00
John McMaster a9c2af5b9d
Merge pull request #470 from mcmasterg/bit_only 
segprint: --bit-only
 2019-01-09 18:43:11 +01:00
John McMaster 010a2eb5da segprint: --bit-only 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2019-01-09 18:36:18 +01:00
Alessandro Comodi 8bdf04a29d 005-tilegrid/add_tdb.py: Added ps7 tdb 
There is an hack to be fixed that selects only the first bit of the
tdb lines. It has to be corrected

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-09 18:14:23 +01:00
Alessandro Comodi 6691d2dcc8 ps7/top.py: updated top generator 
The top.py generates a param.csv file related to a specific tile. The
segdata_tilegrid.tdb related to ps7 now contains two different
addresses bound to a specific tile.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-09 16:31:28 +01:00
Alessandro Comodi b6d68711d8 ps7/Makefile: updated GENERATE_ARGS 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-09 16:30:23 +01:00
Alessandro Comodi 29fbdf595f 005-fuzzer: fix Makefile 
The Makefile now correctly adds the ps7 dependency when zynq7
environment is selected.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-01-09 14:31:42 +01:00