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Merge pull request #487 from antmicro/456_regression_on_CLB_bit 

Bug #456: fix regression in CLB bit CARRY4.ACY0
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John McMaster 2019-01-11 08:23:16 +01:00 committed by GitHub
parent 7eb7d844b1 144a0edc8c
commit b8ced4e5ae
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1 changed files with 18 additions and 2 deletions
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20
fuzzers/013-clb-ncy0/top.py
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@ -60,7 +60,6 @@ module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
@ -84,6 +83,15 @@ module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
endmodule
module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
@ -92,7 +100,6 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
@ -120,5 +127,14 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
endmodule
''')