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7 Commits

Author SHA1 Message Date
Rick Altherr ad150af4df minitests: partial_reconfig_flow: Remove init/final sequence hacks 
Now that xc7series generates proper .bit files, the hacks need to be
removed.

Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-02-01 14:34:31 -08:00
Rick Altherr 6b7af3b168 minitests: partial_reconfig_flow: always save ROI bitstreams 
Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-02-01 14:34:31 -08:00
Rick Altherr f108805a0f partial_reconfig_flow: Rework to allow any verilog for ROI 
Change naming to clarify which files are related to synthesis vs
implementation. Rewrite ROI synthesis and implementation rules as
pattern rules to allow any .v to be used as an ROI design.

Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-01-25 21:10:05 -08:00
John McMaster bb9e8b8dc4 partial_config_flow: fix readme bad commands 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-01-25 17:22:55 -08:00
Rick Altherr b6f754dae7 Document how init_sequence and final_sequence offsets were determined. 
Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-01-22 15:26:17 -08:00
Rick Altherr 554cf549c4 Use .bit and .bin consistently 
Xilinx uses .bit for bitstreams that include an additional header that
appears to carry some build information (tool version, date built, etc).
For bitstreams without that header, they use .bin.

Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-01-22 15:23:48 -08:00
Rick Altherr 425c96c10d minitest: FASM and xc7patch proof of concept using partial reconfig flow 
Harness is implemented using Vivado's Partial Reconfiguration flow.  ROI
designs are generated from FASM and patched into the harness to create a
programmable bitstream.

Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
 2018-01-22 14:15:31 -08:00