mirror of https://github.com/openXC7/prjxray.git
minitest: FASM and xc7patch proof of concept using partial reconfig flow
Harness is implemented using Vivado's Partial Reconfiguration flow. ROI designs are generated from FASM and patched into the harness to create a programmable bitstream. Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
This commit is contained in:
Rick Altherr
parent
86db6b6724
commit
425c96c10d
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# Top-level target for generating a programmable bitstream. Given a .fasm
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# file, calling make with the .fasm extension replaced with .hand_crafted.bit
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# will generate a bitstream that includes both the harness and the .fasm design
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# ready for programming to a board. For example, 'make
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# roi_noninv.hand_crafted.bit' will generate a bitstream that includes the
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# design from roi_noninv.fasm.
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%.hand_crafted.bit: init_sequence.bit %.no_headers.bit final_sequence.bit
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cat $^ > $@
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%.no_headers.bit: %.patched.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x18 $< | xxd -r -p - $@
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%.patched.bit: %.frm harness_routed.bit
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${XRAY_TOOLS_DIR}/xc7patch \
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--part_file ${XRAY_PART_YAML} \
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--bitstream_file harness_routed.bit \
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--frm_file $< \
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--output_file $@
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# xc7patch currently only generates the actual frame writes which is
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# insufficient to program a device. Grab the initialization and finalization
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# sequences from the harness bitstream so they can be tacked on to the
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# xc7patch-generated bitstream to create a programmable bitstream.
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init_sequence.bit: harness_routed.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -l 0x147 $< | xxd -r -p - $@
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final_sequence.bit: harness_routed.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x216abf $< | \
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tr -d '\n' | \
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sed -e 's/30000001.\{8\}/3000800100000007/g' | \
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fold -w 40 | \
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xxd -r -p - $@
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# Generate a suitable harness by using Vivado's partial reconfiguration
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# feature. roi_inv is used as a sample reconfiguration design as one is
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# required to generate a partial reconfiguration design.
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harness.dcp: harness.tcl top.v roi_base.v
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vivado -mode batch -source harness.tcl
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roi_inv.dcp: roi_inv.tcl roi_inv.v
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vivado -mode batch -source roi_inv.tcl
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roi_inv_routed.dcp roi_inv_w_harness_routed.dcp harness_routed.dcp: harness.dcp roi_inv.dcp roi_inv_routed.tcl
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vivado -mode batch -source roi_inv_routed.tcl
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# Conversions between various formats.
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%.bit: %.dcp write_bitstream.tcl
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vivado -mode batch -source write_bitstream.tcl -tclargs $< $@
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%.bits: %.bit
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${XRAY_BITREAD} -y -o $@ $<
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# Extract only bits that are within the ROI.
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%.roi.bits: %.bit
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${XRAY_BITREAD} -F ${XRAY_ROI_FRAMES} -z -y -o $@ $<
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%.segp: %.roi.bits
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${XRAY_SEGPRINT} -zd $< > $@
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%.fasm: %.segp
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${XRAY_DIR}/tools/segprint2fasm.py $< $@
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%.frm: %.fasm
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${XRAY_DIR}/tools/fasm2frame.py $< $@
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%.packets: %.bit
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${XRAY_TOOLS_DIR}/bittool list_config_packets $< > $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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rm -rf out_* *~
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rm -rf *.frm *.segp *.packets
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rm -rf harness_routed.fasm roi_inv_w_harness_routed.fasm
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rm -rf hd_visual
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.PHONY: clean
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@ -0,0 +1,53 @@
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# FASM Proof of Concept using Vivado Partial Reconfig flow
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top.v is a top-level design that routes a variety of signal into a black-box
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region of interest (ROI). Vivado's Partial Reconfiguration flow (see UG909
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and UG947) is used to implement that design and obtain a bitstream that
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configures portions of the chip that are currently undocumented.
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Designs that fit within the ROI are written in FASM and merged with the above
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harness into a bitstream with fasm2frame and xc7patch.
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# Usage
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make rules are provided for generating each step of the process so that
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intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
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the %.hand\_crafted.bit rule will generate a merged bitstream:
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```
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make foo.hand\_crafted.bit # reads foo.fasm
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```
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# Using Vivado to generate .fasm
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Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
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design that is then converted to .fasm. The basic process is to write a module
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that _exactly_ matches the roi blackbox in the top-level design. Note that
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even the name of the module must match exactly. Once you have a design, the
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first step is to synthesize the design with -mode out\_of\_context:
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```
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read_verilog <design>.v
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synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
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write_checkpoint -force <design>.dcp
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```
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Next, implement that design within the harness. Run 'make harness\_routed.dcp'
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if it doesn't already exist. The following TCL will load the fully-routed
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harness, load your synthesized design, and generate a bitstream containing
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both:
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```
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open_checkpoint -force harness_routed.dcp
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read_checkpoint -cell <design>.dcp
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opt_design
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place_design
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route_design
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write_checkpoint -force <design>_routed.dcp
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write_bitstream -force <design>_routed.bit
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```
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'make <design>\_routed.fasm' will run a sequence of tools to extract the bits
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that are inside the ROI and convert them to FASM. The resulting .fasm can be
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used to generate a marged bitstream using
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'make <design>\_routed.hand\_crafted.bit'. The resulting bitstream should be
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equivalent to <design>\_routed.bit.
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`ifndef DIN_N
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`define DIN_N 8
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`endif
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`ifndef DOUT_N
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`define DOUT_N 8
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`endif
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read_verilog top.v
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read_verilog roi_base.v
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synth_design -top top -part $::env(XRAY_PART)
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write_checkpoint -force harness.dcp
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//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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endmodule
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read_verilog roi_inv.v
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synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
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write_checkpoint -force roi_inv.dcp
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//Connect the switches to the LEDs, inverting the signal in the ROI
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//Assumes # inputs = # outputs
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire [DIN_N-1:0] internal;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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//Very expensive inverter
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(internal[i]));
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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//Very expensive buffer
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b010)
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) lut (
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.I0(internal[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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open_checkpoint harness.dcp
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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# Number of package inputs going to ROI
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set DIN_N 8
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# Number of ROI outputs going to package
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set DOUT_N 8
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set part $::env(XRAY_PART)
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set pincfg $::env(XRAY_PINCFG)
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# Map of top level net names to IOB pin names
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array set net2pin [list]
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# Create pin assignments based on what we are targetting
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# A50T I/O Bank 16 sequential layout
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if {$part eq "xc7a50tfgg484-1"} {
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# Partial list, expand as needed
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set bank_16 "F21 G22 G21 D21 E21 D22 E22 A21 B21 B22 C22 C20 D20 F20 F19 A19 A18"
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set banki 0
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# CLK
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set pin [lindex $bank_16 $banki]
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incr banki
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set net2pin(clk) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $bank_16 $banki]
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incr banki
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $bank_16 $banki]
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incr banki
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set net2pin(dout[$i]) $pin
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}
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# Arty A7 switch, button, and LED
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if {$pincfg eq "ARTY-A7-SWBUT"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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# 4 switches then 4 buttons
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set sw_but "A8 C11 C10 A10 D9 C9 B9 B8"
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# 4 LEDs then 4 RGB LEDs (green only)
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set leds "H5 J5 T9 T10 F6 J4 J2 H6"
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# 100 MHz CLK onboard
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set pin "E3"
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set net2pin(clk) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sw_but $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$pincfg eq "ARTY-A7-PMOD"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# CLK on Pmod JA
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set pin [lindex $pmod_ja 0]
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set net2pin(clk) $pin
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# DIN on Pmod JB
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT on Pmod JC
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set net2pin(dout[$i]) $pin
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}
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} else {
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error "Unsupported config $pincfg"
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}
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} elseif {$part eq "xc7a35tcpg236-1"} {
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if {$pincfg eq "BASYS3-SWBUT"} {
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# https://raw.githubusercontent.com/Digilent/digilent-xdc/master/Basys-3-Master.xdc
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# Slide switches
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set sws "V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2"
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set leds "U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1"
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# 100 MHz CLK onboard
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set pin "W5"
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set net2pin(clk) $pin
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sws $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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} else {
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error "Unsupported config $pincfg"
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}
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} else {
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error "Pins: unsupported part $part"
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}
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# Now actually apply the pin definitions
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puts "Applying pin definitions"
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foreach {net pin} [array get net2pin] {
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puts " Net $net to pin $pin"
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports $net]
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}
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set_property HD.RECONFIGURABLE TRUE [get_cells roi]
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read_checkpoint -cell roi roi_inv.dcp
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opt_design
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place_design
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route_design
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write_checkpoint -force roi_inv_w_harness_routed.dcp
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# Routed design of roi cell only
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write_checkpoint -force -cell roi roi_inv_routed.dcp
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# Replace roi cell with a black box and write the rest of the design
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update_design -cell roi -black_box
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lock_design -level routing
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write_checkpoint -force harness_routed.dcp
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@ -0,0 +1,228 @@
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INT_L_X10Y107.CENTER_INTER_L.SE6BEG0 NN6END0
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INT_L_X10Y104.CENTER_INTER_L.WL1BEG0 NW2END2
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INT_L_X10Y103.CENTER_INTER_L.EL1BEG0 NR1END1
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INT_L_X10Y103.CENTER_INTER_L.EL1BEG_N3 NW2END0
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INT_L_X10Y103.CENTER_INTER_L.FAN_ALT4 NR1END0
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INT_L_X10Y103.CENTER_INTER_L.NE2BEG3 NL1BEG_N3
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INT_L_X10Y103.CENTER_INTER_L.NL1BEG_N3 NL1END0
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INT_L_X10Y103.CENTER_INTER_L.SE2BEG2 EL1END2
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INT_L_X10Y103.CENTER_INTER_L.WW2BEG2 WL1END2
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CLBLM_L_X10Y102.SLICE_X13Y102.ALUT.INIT[01] 1
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CLBLM_L_X10Y102.SLICE_X13Y102.BLUT.INIT[01] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[01] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.BLUT.INIT[01] 1
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INT_L_X10Y102.CENTER_INTER_L.BYP_ALT5 NN2END2
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INT_L_X10Y102.CENTER_INTER_L.EE2BEG2 NL1END2
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INT_L_X10Y102.CENTER_INTER_L.EL1BEG_N3 NL1END0
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INT_L_X10Y102.CENTER_INTER_L.GFAN0 GND_WIRE
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INT_L_X10Y102.CENTER_INTER_L.GFAN1 GND_WIRE
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L0 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L10 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L11 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L12 GFAN1
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L13 GFAN1
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L14 NL1BEG_N3
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L15 FAN_BOUNCE_S3_4
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L16 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L17 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L18 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L19 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L2 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L24 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L25 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L26 GFAN0
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INT_L_X10Y102.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L6 WR1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE5
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L13
|
||||
INT_L_X10Y102.CENTER_INTER_L.SE2BEG2 EL1END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.SR1BEG2 WL1END1
|
||||
INT_L_X10Y102.CENTER_INTER_L.SW2BEG3 WL1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.WW2BEG2 WL1END2
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.BLUT.INIT[01] 1
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT4 NW2END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.ER1BEG2 LOGIC_OUTS_L13
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L12 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L14 SR1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L15 BYP_BOUNCE3
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L17 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L18 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L24 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L6 BYP_BOUNCE4
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L7 NW2END_S0_0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.LV_L18 SR1BEG_S0
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG1 NR1END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG3 NN6END3
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG2 WL1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y101.CENTER_INTER_L.NN6BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y101.CENTER_INTER_L.SE2BEG2 EE2END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X12Y100.ALUT.INIT[01] 1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT1 LOGIC_OUTS_L8
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT2 BYP_BOUNCE1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y100.CENTER_INTER_L.EE2BEG3 NN6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L14 BYP_BOUNCE2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L6 SW2END2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE3
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG3 NE6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NL1BEG_N3 WL1END_N1_3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NN2BEG2 WL1END1
|
||||
INT_L_X10Y100.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L9
|
||||
INT_L_X10Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X11Y104.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.NW2BEG2 NN2END2
|
||||
INT_R_X11Y103.CENTER_INTER_R.SL1BEG0 EL1END0
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG2 SL1END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG_N3 WR1END1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.BLUT.INIT[01] 1
|
||||
INT_R_X11Y102.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX7 WR1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.NW2BEG0 LOGIC_OUTS12
|
||||
INT_R_X11Y102.CENTER_INTER_R.SE2BEG1 NE2END1
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG2 SE2END2
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG1 NW2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG2 WL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG_N3 SL1END0
|
||||
INT_R_X11Y102.CENTER_INTER_R.WR1BEG3 NR1END2
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.AMUX.O6 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.BLUT.INIT[01] 1
|
||||
INT_R_X11Y101.CENTER_INTER_R.EE2BEG2 ER1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX7 NR1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.NN2BEG2 LOGIC_OUTS20
|
||||
INT_R_X11Y101.CENTER_INTER_R.NR1BEG2 SE2END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.NW2BEG0 NE2END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SW2BEG2 SL1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG2 WR1END_S1_0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG0 WL1END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG1 WL1END1
|
||||
CLBLM_R_X11Y100.SLICE_X14Y100.ALUT.INIT[01] 1
|
||||
INT_R_X11Y100.CENTER_INTER_R.BYP_ALT5 ER1END1
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX7 BYP_BOUNCE5
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.NL1BEG_N3 LOGIC_OUTS12
|
||||
INT_R_X11Y100.CENTER_INTER_R.NR1BEG3 NL1BEG_N3
|
||||
INT_R_X11Y100.CENTER_INTER_R.NW2BEG1 WL1END0
|
||||
INT_R_X11Y100.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG1 SE2END2
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WL1BEG_N3 SE6END0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WR1BEG1 NR1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.NR1BEG0 EL1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.WR1BEG3 EE2END2
|
||||
INT_L_X12Y101.CENTER_INTER_L.NW2BEG3 NR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.SE2BEG0 EL1END0
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG0 SE2END1
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG1 WR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.WR1BEG_S0 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.EL1BEG2 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.LV_L18 WR1END0
|
||||
INT_L_X12Y100.CENTER_INTER_L.NR1BEG3 EE2END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.SW6BEG3 LV_L18
|
||||
INT_L_X12Y100.CENTER_INTER_L.WL1BEG0 WR1END2
|
||||
INT_R_X13Y101.CENTER_INTER_R.WR1BEG3 EE2END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.SL1BEG2 EL1END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.WL1BEG_N3 SE2END0
|
||||
INT_R_X13Y100.CENTER_INTER_R.WR1BEG2 NR1END1
|
||||
INT_L_X16Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X16Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X17Y101.CENTER_INTER_R.WL1BEG_N3 WW2END0
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.DMUX.AX 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZINI 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZRST 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.FFSYNC 1
|
||||
INT_R_X17Y100.CENTER_INTER_R.BYP_ALT0 LOGIC_OUTS0
|
||||
INT_R_X17Y100.CENTER_INTER_R.CLK0 ER1END1
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
//See README and tcl for more info
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module top(input wire clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = `DIN_N;
|
||||
parameter DOUT_N = `DOUT_N;
|
||||
|
||||
roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N)) roi (
|
||||
.clk(clk),
|
||||
.din(din), .dout(dout));
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
open_checkpoint [lindex $argv 0]
|
||||
|
||||
# Disabling CRC just replaces the CRC register writes with Reset CRC commands.
|
||||
# This seems to work via JTAG as it works in combination with PERFRAMECRC
|
||||
# either when applied via Vivado (this setting) or by manually patching the
|
||||
# bitstream later.
|
||||
#
|
||||
set_property BITSTREAM.GENERAL.CRC Disable [current_design]
|
||||
|
||||
# Debug bitstreams write to LOUT which is only valid on serial master/slave
|
||||
# programming methods. If those are replaced with NOPs, Reset CRC commands, or
|
||||
# removed entirely, the bitstream will program (DONE light goes active) but the
|
||||
# configuration doesn't start. The JTAG status register shows BAD_PACKET_ERROR
|
||||
# when this happens. I'm guessing that the individual frame writes require the
|
||||
# PERFRAMECRC approach to work at all via JTAG.
|
||||
#
|
||||
#set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
|
||||
|
||||
# PERFRAMECRC bitstreams can be directly loaded via JTAG. They also use an
|
||||
# undocumented bit to disable autoincrement which seems to be required if doing
|
||||
# individual frame writes instead of a bulk write. The CRC chceks after each
|
||||
# frame are _required_ for this bitstream to program.
|
||||
#
|
||||
#set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
|
||||
write_bitstream -force [lindex $argv 1]
|
||||
Loading…
Reference in New Issue