mirror of https://github.com/openXC7/prjxray.git
partial_reconfig_flow: Rework to allow any verilog for ROI
Change naming to clarify which files are related to synthesis vs implementation. Rewrite ROI synthesis and implementation rules as pattern rules to allow any .v to be used as an ROI design. Signed-off-by: Rick Altherr <kc8apf@kc8apf.net>
This commit is contained in:
Rick Altherr
parent
bf438aceed
commit
f108805a0f
|
|
@ -1,21 +1,23 @@
|
|||
.PRECIOUS: harness_impl.dcp %_impl.dcp %.bit
|
||||
|
||||
# Top-level target for generating a programmable bitstream. Given a .fasm
|
||||
# file, calling make with the .fasm extension replaced with .hand_crafted.bit
|
||||
# file, calling make with the .fasm extension replaced with _hand_crafted.bit
|
||||
# will generate a bitstream that includes both the harness and the .fasm design
|
||||
# ready for programming to a board. For example, 'make
|
||||
# roi_noninv.hand_crafted.bit' will generate a bitstream that includes the
|
||||
# ready for programming to a board. For example,
|
||||
# 'make inv_hand_crafted.bit' will generate a bitstream that includes the
|
||||
# design from roi_noninv.fasm.
|
||||
%.hand_crafted.bit: init_sequence.bit %.no_headers.bin final_sequence.bin
|
||||
%_hand_crafted.bit: init_sequence.bit %_no_headers.bin final_sequence.bin
|
||||
cat $^ > $@
|
||||
|
||||
%.no_headers.bin: %.patched.bin
|
||||
%_no_headers.bin: %_patched.bin
|
||||
# WARNING: these values need to be tweaked if anything about the
|
||||
# Vivado-generated design changes.
|
||||
xxd -p -s 0x18 $< | xxd -r -p - $@
|
||||
|
||||
%.patched.bin: %.frm harness_routed.bit
|
||||
%_patched.bin: %_roi_partial.frm harness.bit
|
||||
${XRAY_TOOLS_DIR}/xc7patch \
|
||||
--part_file ${XRAY_PART_YAML} \
|
||||
--bitstream_file harness_routed.bit \
|
||||
--bitstream_file harness.bit \
|
||||
--frm_file $< \
|
||||
--output_file $@
|
||||
|
||||
|
|
@ -25,7 +27,7 @@
|
|||
# xc7patch-generated bitstream to create a programmable bitstream.
|
||||
#
|
||||
# The offsets used below were determined by manually inspecting
|
||||
# harness_routed.bit with a hex editor. init_sequence.bit is the beginning of
|
||||
# harness.bit with a hex editor. init_sequence.bit is the beginning of
|
||||
# the file until just before the actual frame data is sent via a write to FDRI.
|
||||
# final_sequence.bin is from just after the frame data write to the end of the
|
||||
# file. Note that final_sequence.bin normally includes at least one CRC check.
|
||||
|
|
@ -33,12 +35,12 @@
|
|||
# same behavior as setting BITSTREAM.GENERAL.CRC to Disabled. These offset
|
||||
# should not change unless you alter the bitstream format used (i.e. setting
|
||||
# BITSTREAM.GENERAL.DEBUGBITSTREAM or BITSTREAM.GENERAL.PERFRAMECRC to YES).
|
||||
init_sequence.bit: harness_routed.bit
|
||||
init_sequence.bit: harness.bit
|
||||
# WARNING: these values need to be tweaked if anything about the
|
||||
# Vivado-generated design changes.
|
||||
xxd -p -l 0x147 $< | xxd -r -p - $@
|
||||
|
||||
final_sequence.bin: harness_routed.bit
|
||||
final_sequence.bin: harness.bit
|
||||
# WARNING: these values need to be tweaked if anything about the
|
||||
# Vivado-generated design changes.
|
||||
xxd -p -s 0x216abf $< | \
|
||||
|
|
@ -48,29 +50,35 @@ final_sequence.bin: harness_routed.bit
|
|||
xxd -r -p - $@
|
||||
|
||||
# Generate a suitable harness by using Vivado's partial reconfiguration
|
||||
# feature. roi_inv is used as a sample reconfiguration design as one is
|
||||
# feature. inv.v is used as a sample reconfiguration design as one is
|
||||
# required to generate a partial reconfiguration design.
|
||||
harness.dcp: harness.tcl top.v roi_base.v
|
||||
vivado -mode batch -source harness.tcl
|
||||
harness_synth.dcp: harness_synthesize.tcl harness.v
|
||||
vivado -mode batch -source harness_synthesize.tcl
|
||||
|
||||
roi_inv.dcp: roi_inv.tcl roi_inv.v
|
||||
vivado -mode batch -source roi_inv.tcl
|
||||
harness_impl.dcp: harness_synth.dcp inv_synth.dcp harness_implement.tcl
|
||||
vivado -mode batch -source harness_implement.tcl
|
||||
|
||||
roi_inv_routed.dcp roi_inv_w_harness_routed.dcp harness_routed.dcp: harness.dcp roi_inv.dcp roi_inv_routed.tcl
|
||||
vivado -mode batch -source roi_inv_routed.tcl
|
||||
# Synthesize an ROI design
|
||||
%_synth.dcp: %.v roi_synthesize.tcl
|
||||
vivado -mode batch -source roi_synthesize.tcl -tclargs $< $@
|
||||
|
||||
# Implement an ROI design
|
||||
%_impl.dcp: %_synth.dcp harness_impl.dcp roi_implement.tcl
|
||||
vivado -mode batch -source roi_implement.tcl -tclargs $< $@
|
||||
|
||||
# Generate bitstreams from an implemented design. Two bitstreams are
|
||||
# generated: one containing a complete design including the harness (.bit) and
|
||||
# one that only contains the frames that implement the ROI design
|
||||
# (_roi_partial.bit).
|
||||
%.bit: %_impl.dcp write_bitstream.tcl
|
||||
vivado -mode batch -source write_bitstream.tcl -tclargs $< $@
|
||||
%_roi_partial.bit: %.bit ;
|
||||
|
||||
# Conversions between various formats.
|
||||
%.bit: %.dcp write_bitstream.tcl
|
||||
vivado -mode batch -source write_bitstream.tcl -tclargs $< $@
|
||||
|
||||
%.bits: %.bit
|
||||
${XRAY_BITREAD} -y -o $@ $<
|
||||
${XRAY_BITREAD} -z -y -o $@ $<
|
||||
|
||||
# Extract only bits that are within the ROI.
|
||||
%.roi.bits: %.bit
|
||||
${XRAY_BITREAD} -F ${XRAY_ROI_FRAMES} -z -y -o $@ $<
|
||||
|
||||
%.segp: %.roi.bits
|
||||
%.segp: %.bits
|
||||
${XRAY_SEGPRINT} -zd $< > $@
|
||||
|
||||
%.fasm: %.segp
|
||||
|
|
@ -85,10 +93,8 @@ roi_inv_routed.dcp roi_inv_w_harness_routed.dcp harness_routed.dcp: harness.dcp
|
|||
${XRAY_TOOLS_DIR}/bittool list_config_packets $< > $@
|
||||
|
||||
clean:
|
||||
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
|
||||
rm -rf out_* *~
|
||||
rm -rf *.frm *.segp *.packets *.bin
|
||||
rm -rf harness_routed.fasm roi_inv_w_harness_routed.fasm
|
||||
rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
|
||||
rm -rf *.frm *.segp *.packets *.bin *.fasm
|
||||
rm -rf hd_visual
|
||||
|
||||
.PHONY: clean
|
||||
|
|
|
|||
|
|
@ -1,18 +1,20 @@
|
|||
# FASM Proof of Concept using Vivado Partial Reconfig flow
|
||||
|
||||
top.v is a top-level design that routes a variety of signal into a black-box
|
||||
harness.v is a top-level design that routes a variety of signal into a black-box
|
||||
region of interest (ROI). Vivado's Partial Reconfiguration flow (see UG909
|
||||
and UG947) is used to implement that design and obtain a bitstream that
|
||||
configures portions of the chip that are currently undocumented.
|
||||
|
||||
Designs that fit within the ROI are written in FASM and merged with the above
|
||||
harness into a bitstream with fasm2frame and xc7patch.
|
||||
harness into a bitstream with fasm2frame and xc7patch. Since writting FASM is
|
||||
rather tedious, rules are provided to convert Verilog ROI designs into FASM via
|
||||
Vivado.
|
||||
|
||||
# Usage
|
||||
|
||||
make rules are provided for generating each step of the process so that
|
||||
intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
|
||||
the %.hand\_crafted.bit rule will generate a merged bitstream:
|
||||
the %\_hand\_crafted.bit rule will generate a merged bitstream:
|
||||
|
||||
```
|
||||
make foo.hand\_crafted.bit # reads foo.fasm
|
||||
|
|
@ -21,33 +23,11 @@ make foo.hand\_crafted.bit # reads foo.fasm
|
|||
# Using Vivado to generate .fasm
|
||||
|
||||
Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
|
||||
design that is then converted to .fasm. The basic process is to write a module
|
||||
that _exactly_ matches the roi blackbox in the top-level design. Note that
|
||||
even the name of the module must match exactly. Once you have a design, the
|
||||
first step is to synthesize the design with -mode out\_of\_context:
|
||||
|
||||
```
|
||||
read_verilog <design>.v
|
||||
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
|
||||
write_checkpoint -force <design>.dcp
|
||||
```
|
||||
|
||||
Next, implement that design within the harness. Run 'make harness\_routed.dcp'
|
||||
if it doesn't already exist. The following TCL will load the fully-routed
|
||||
harness, load your synthesized design, and generate a bitstream containing
|
||||
both:
|
||||
```
|
||||
open_checkpoint harness_routed.dcp
|
||||
read_checkpoint -cell roi <design>.dcp
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_checkpoint -force <design>_routed.dcp
|
||||
write_bitstream -force <design>_routed.bit
|
||||
```
|
||||
|
||||
'make <design>\_routed.fasm' will run a sequence of tools to extract the bits
|
||||
that are inside the ROI and convert them to FASM. The resulting .fasm can be
|
||||
used to generate a marged bitstream using
|
||||
'make <design>\_routed.hand\_crafted.bit'. The resulting bitstream should be
|
||||
equivalent to <design>\_routed.bit.
|
||||
ROI design that is then converted to .fasm. Write a Verilog module
|
||||
that _exactly_ matches the roi blackbox model in the top-level design. Note
|
||||
that even the name of the module must match exactly. Assuming you have created
|
||||
that design in my\_roi\_design.v, 'make my\_roi\_design\_hand\_crafted.bit'
|
||||
will synthesize and implement the design with Vivado, translate the resulting
|
||||
partial bitstream into FASM, and then generate a full bitstream by patching the
|
||||
harness bitstream with the FASM. non\_inv.v is provided as an example ROI
|
||||
design for this flow.
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
read_verilog top.v
|
||||
read_verilog roi_base.v
|
||||
|
||||
synth_design -top top -part $::env(XRAY_PART)
|
||||
write_checkpoint -force harness.dcp
|
||||
|
|
@ -1,7 +1,11 @@
|
|||
//See README and tcl for more info
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module roi(input clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = `DIN_N;
|
||||
parameter DOUT_N = `DOUT_N;
|
||||
endmodule
|
||||
|
||||
module top(input wire clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = `DIN_N;
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
open_checkpoint harness.dcp
|
||||
open_checkpoint harness_synth.dcp
|
||||
|
||||
create_pblock roi
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
|
|
@ -132,18 +132,13 @@ foreach {net pin} [array get net2pin] {
|
|||
|
||||
set_property HD.RECONFIGURABLE TRUE [get_cells roi]
|
||||
|
||||
read_checkpoint -cell roi roi_inv.dcp
|
||||
read_checkpoint -cell roi inv_synth.dcp
|
||||
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force roi_inv_w_harness_routed.dcp
|
||||
|
||||
# Routed design of roi cell only
|
||||
write_checkpoint -force -cell roi roi_inv_routed.dcp
|
||||
|
||||
# Replace roi cell with a black box and write the rest of the design
|
||||
update_design -cell roi -black_box
|
||||
lock_design -level routing
|
||||
write_checkpoint -force harness_routed.dcp
|
||||
write_checkpoint -force harness_impl.dcp
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
read_verilog harness.v
|
||||
synth_design -top top -part $::env(XRAY_PART)
|
||||
write_checkpoint -force harness_synth.dcp
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
//Connect the switches to the LEDs, inverting the signal in the ROI
|
||||
//Assumes # inputs = # outputs
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module roi(input clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = `DIN_N;
|
||||
parameter DOUT_N = `DOUT_N;
|
||||
wire [DIN_N-1:0] internal;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
//CLK
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
reg clk_reg;
|
||||
always @(posedge clk) begin
|
||||
clk_reg <= clk_reg;
|
||||
end
|
||||
|
||||
//DIN
|
||||
for (i = 0; i < DIN_N; i = i+1) begin:ins
|
||||
//Very expensive inverter
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 #(
|
||||
.INIT(64'b10)
|
||||
) lut (
|
||||
.I0(din[i]),
|
||||
.I1(1'b0),
|
||||
.I2(1'b0),
|
||||
.I3(1'b0),
|
||||
.I4(1'b0),
|
||||
.I5(1'b0),
|
||||
.O(internal[i]));
|
||||
end
|
||||
|
||||
//DOUT
|
||||
for (i = 0; i < DOUT_N; i = i+1) begin:outs
|
||||
//Very expensive buffer
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 #(
|
||||
.INIT(64'b010)
|
||||
) lut (
|
||||
.I0(internal[i]),
|
||||
.I1(1'b0),
|
||||
.I2(1'b0),
|
||||
.I3(1'b0),
|
||||
.I4(1'b0),
|
||||
.I5(1'b0),
|
||||
.O(dout[i]));
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
//See README and tcl for more info
|
||||
|
||||
`include "defines.v"
|
||||
|
||||
module roi(input clk,
|
||||
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
|
||||
parameter DIN_N = `DIN_N;
|
||||
parameter DOUT_N = `DOUT_N;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
open_checkpoint harness_impl.dcp
|
||||
read_checkpoint -cell roi [lindex $argv 0]
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_checkpoint -force [lindex $argv 1]
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog roi_inv.v
|
||||
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
|
||||
write_checkpoint -force roi_inv.dcp
|
||||
|
|
@ -1,228 +0,0 @@
|
|||
INT_L_X10Y107.CENTER_INTER_L.SE6BEG0 NN6END0
|
||||
INT_L_X10Y104.CENTER_INTER_L.WL1BEG0 NW2END2
|
||||
INT_L_X10Y103.CENTER_INTER_L.EL1BEG0 NR1END1
|
||||
INT_L_X10Y103.CENTER_INTER_L.EL1BEG_N3 NW2END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.FAN_ALT4 NR1END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.NE2BEG3 NL1BEG_N3
|
||||
INT_L_X10Y103.CENTER_INTER_L.NL1BEG_N3 NL1END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.SE2BEG2 EL1END2
|
||||
INT_L_X10Y103.CENTER_INTER_L.WW2BEG2 WL1END2
|
||||
CLBLM_L_X10Y102.SLICE_X13Y102.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X13Y102.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.BLUT.INIT[01] 1
|
||||
INT_L_X10Y102.CENTER_INTER_L.BYP_ALT5 NN2END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.EE2BEG2 NL1END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.EL1BEG_N3 NL1END0
|
||||
INT_L_X10Y102.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y102.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L12 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L14 NL1BEG_N3
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L15 FAN_BOUNCE_S3_4
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L17 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L18 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L24 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L6 WR1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE5
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L13
|
||||
INT_L_X10Y102.CENTER_INTER_L.SE2BEG2 EL1END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.SR1BEG2 WL1END1
|
||||
INT_L_X10Y102.CENTER_INTER_L.SW2BEG3 WL1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.WW2BEG2 WL1END2
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.BLUT.INIT[01] 1
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT4 NW2END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.ER1BEG2 LOGIC_OUTS_L13
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L12 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L14 SR1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L15 BYP_BOUNCE3
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L17 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L18 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L24 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L6 BYP_BOUNCE4
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L7 NW2END_S0_0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.LV_L18 SR1BEG_S0
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG1 NR1END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG3 NN6END3
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG2 WL1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y101.CENTER_INTER_L.NN6BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y101.CENTER_INTER_L.SE2BEG2 EE2END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X12Y100.ALUT.INIT[01] 1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT1 LOGIC_OUTS_L8
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT2 BYP_BOUNCE1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y100.CENTER_INTER_L.EE2BEG3 NN6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L14 BYP_BOUNCE2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L6 SW2END2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE3
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG3 NE6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NL1BEG_N3 WL1END_N1_3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NN2BEG2 WL1END1
|
||||
INT_L_X10Y100.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L9
|
||||
INT_L_X10Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X11Y104.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.NW2BEG2 NN2END2
|
||||
INT_R_X11Y103.CENTER_INTER_R.SL1BEG0 EL1END0
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG2 SL1END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG_N3 WR1END1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.BLUT.INIT[01] 1
|
||||
INT_R_X11Y102.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX7 WR1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.NW2BEG0 LOGIC_OUTS12
|
||||
INT_R_X11Y102.CENTER_INTER_R.SE2BEG1 NE2END1
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG2 SE2END2
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG1 NW2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG2 WL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG_N3 SL1END0
|
||||
INT_R_X11Y102.CENTER_INTER_R.WR1BEG3 NR1END2
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.AMUX.O6 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.BLUT.INIT[01] 1
|
||||
INT_R_X11Y101.CENTER_INTER_R.EE2BEG2 ER1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX7 NR1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.NN2BEG2 LOGIC_OUTS20
|
||||
INT_R_X11Y101.CENTER_INTER_R.NR1BEG2 SE2END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.NW2BEG0 NE2END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SW2BEG2 SL1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG2 WR1END_S1_0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG0 WL1END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG1 WL1END1
|
||||
CLBLM_R_X11Y100.SLICE_X14Y100.ALUT.INIT[01] 1
|
||||
INT_R_X11Y100.CENTER_INTER_R.BYP_ALT5 ER1END1
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX7 BYP_BOUNCE5
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.NL1BEG_N3 LOGIC_OUTS12
|
||||
INT_R_X11Y100.CENTER_INTER_R.NR1BEG3 NL1BEG_N3
|
||||
INT_R_X11Y100.CENTER_INTER_R.NW2BEG1 WL1END0
|
||||
INT_R_X11Y100.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG1 SE2END2
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WL1BEG_N3 SE6END0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WR1BEG1 NR1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.NR1BEG0 EL1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.WR1BEG3 EE2END2
|
||||
INT_L_X12Y101.CENTER_INTER_L.NW2BEG3 NR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.SE2BEG0 EL1END0
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG0 SE2END1
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG1 WR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.WR1BEG_S0 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.EL1BEG2 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.LV_L18 WR1END0
|
||||
INT_L_X12Y100.CENTER_INTER_L.NR1BEG3 EE2END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.SW6BEG3 LV_L18
|
||||
INT_L_X12Y100.CENTER_INTER_L.WL1BEG0 WR1END2
|
||||
INT_R_X13Y101.CENTER_INTER_R.WR1BEG3 EE2END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.SL1BEG2 EL1END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.WL1BEG_N3 SE2END0
|
||||
INT_R_X13Y100.CENTER_INTER_R.WR1BEG2 NR1END1
|
||||
INT_L_X16Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X16Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X17Y101.CENTER_INTER_R.WL1BEG_N3 WW2END0
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.DMUX.AX 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZINI 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZRST 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.FFSYNC 1
|
||||
INT_R_X17Y100.CENTER_INTER_R.BYP_ALT0 LOGIC_OUTS0
|
||||
INT_R_X17Y100.CENTER_INTER_R.CLK0 ER1END1
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
read_verilog [lindex $argv 0]
|
||||
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
|
||||
write_checkpoint -force [lindex $argv 1]
|
||||
|
||||
Loading…
Reference in New Issue