A SING-row sibling of 036-iob18-ologic. The parent fuzzer filters
to IOB18S / IOB18M (diff-pair main / secondary), leaving the IOB18
site type in *_SING tiles uncharacterised. This fuzzer's filter
is the complement: only the IOB18 site type, only in *_SING
tiles. Pushes to lioi_sing / rioi_sing via the two new mergedb
modes.
utils/mergedb.sh: add the two missing modes. The captured
specimens emit LIOI_SING. and RIOI_SING. entries in the same
file; the new cases grep each side into its own merge target so
the existing segbits_lioi_sing.db / segbits_rioi_sing.db are
populated symmetrically without needing to refactor the fuzzer
into two passes.
Note: the SING-tile frame layout has 2 words (offsets 99..100),
so OLOGIC features at word offsets 30+ within the regular LIOI
tile cannot be straightforwardly mirrored. The 10 features the
fuzzer captures (ZINV_CLK, ODDR/OSERDES SRTYPE/TSRTYPE, OSERDES
DATA_WIDTH variants) all land within the SING tile's two-word
window. The OMUX.D1 / OQUSED / OSERDES.DATA_RATE_TQ.BUF features
nextpnr-xilinx emits for transparent OBUF route-thrus on V7
SING-row IOBs (VC707 led[?] @ LIOI_SING_X82Y51) still need a
separate solution -- they likely live in an aliased frame
through the neighbouring full LIOI tile. Tracking that as a
separate follow-up.
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.
Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README
Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region
General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
install doesn't expose the repo-root utils/ package)
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
The previous xc7s50t branch was messed up. This new branch is created to re-submit xc7s50t's changes for merging.
Signed-off-by: Steve <steve.bohan.liu@outlook.com>
The resources.yaml file does not exists at the beginning of the db-prepare calls
but the environment wants to read it which leads to the following error:
Preparing artix7 files
============================
Traceback (most recent call last):
File ".../prjxray/utils/create_environment.py", line 62, in <module>
main()
File ".../prjxray/utils/create_environment.py", line 55, in main
environment = get_environment_variables()
File ".../prjxray/utils/create_environment.py", line 37, in get_environment_variables
part_info = get_part_information(db_root, part)
File ".../prjxray/prjxray/util.py", line 44, in get_part_information
"Mapping file {} does not exists".format(filename)
AssertionError: Mapping file .../prjxray/database/artix7/mapping/parts.yaml does not exists
Do not dump the environment during this stage because the XRAY_PART is the only
neccessary information which is set in the <family>.sh script.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
* Adds a new tool to update the parts mapping file for a family.
* Adds a new tool to update the resource file for a family.
* Adds a new tool to roi all parts by calling "make roi_only" with different
parts
Update the Makefile to update the artix7 files with "make db-update".
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Problems found:
- for some PIPs configurations, no bit is generated. For instance if
there are only connections with RX/TX from the GTP channel
- some missing PIPs with one bit only
- re-routing now correctly runs for every PIP
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Since the tilegrid.json file is not anymore placed inside the part directory,
the test needs to be updated slightly to work with the new structure.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
From the official PyYAML documentation:
"Warning: It is not safe to call yaml.load with any data received from an
untrusted source! yaml.load is as powerful as pickle.load and so may call
any Python function. Check the yaml.safe_load function though."
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Set localisation settings to default values to prevent different locale
results from tools.
Example: Non-English speaking countries use a comma as decimal seperators but
Python's float convert only accepts a point.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Dr Jonathan Richard Robert Kimmitt
Hans Baier
Hans Baier
Adrien Prost-Boucle
Alessandro Comodi
Steve
litghost
Daniel Schultz
Jan Kowalewski
Maciej Kurc
Andrew Butt
Tim Ansell
Tomasz Michalak