mirror of https://github.com/openXC7/prjxray.git
065-gtp-common-pips: add fuzzer to document GTP_COMMON_MID pips
Problems found: - for some PIPs configurations, no bit is generated. For instance if there are only connections with RX/TX from the GTP channel - some missing PIPs with one bit only - re-routing now correctly runs for every PIP Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
2262775279
commit
6e95748068
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@ -0,0 +1,56 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=gtp_common
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PIPLIST_TCL=$(FUZDIR)/gtp_common_pip_list.tcl
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TODO_RE=".*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides ""
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N = 20
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SEGMATCH_FLAGS=-c 2
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SPECIMENS_DEPS=build/cmt_regions.csv
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A_PIPLIST=gtp_common.txt
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include ../pip_loop.mk
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build/segbits_gtp_common.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_gtp_common.rdb \
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$(shell find build -name segdata_gtp_common*.txt)
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RDBS = build/segbits_gtp_common.rdb
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_gtp_common.rdb \
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--seg-fn-out build/segbits_gtp_common.db
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# Keep a copy to track iter progress
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cp build/segbits_gtp_common.rdb build/$(ITER)/segbits_gtp_common.rdb
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cp build/segbits_gtp_common.db build/$(ITER)/segbits_gtp_common.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} gtp_common build/segbits_gtp_common.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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pushdb: database
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${XRAY_MERGEDB} gtp_common_mid_left build/segbits_gtp_common.db
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${XRAY_MERGEDB} gtp_common_mid_right build/segbits_gtp_common.db
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run:
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$(MAKE) clean
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+$(FUZDIR)/../int_loop.sh --check-args "--zero-entries --timeout-iters 10"
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touch run.${XRAY_PART}.ok
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.PHONY: database pushdb run
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@ -0,0 +1,102 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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word = int(word / 32)
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if frame not in [0, 1, 2, 3, 4, 5, 6, 7]:
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return False
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if word != 50:
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return False
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return True
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def read_pip_data(pipfile, pipdata, tile_ports):
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'gtp_common', pipfile)) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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read_pip_data('gtp_common.txt', pipdata, tile_ports)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('GTP_COMMON_MID'):
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata["GTP_COMMON_MID_LEFT"]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,396 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc load_todo {{dir "dst"}} {
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set fp [open "../../todo_all.txt" r]
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# Create map of pip source to remaining destinations for that pip
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set todo_map [dict create]
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for {gets $fp line} {$line != ""} {gets $fp line} {
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set parts [split $line .]
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if {$dir == "dsts"} {
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dict lappend todo_map [lindex $parts 2] [list [lindex $parts 0] [lindex $parts 1]]
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} elseif {$dir == "srcs"} {
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dict lappend todo_map [lindex $parts 1] [list [lindex $parts 0] [lindex $parts 2]]
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} else {
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error "Incorrect argument. Available options: src, dst"
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}
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}
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close $fp
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return $todo_map
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}
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proc shuffle_list {list} {
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set l [llength $list]
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for {set i 0} {$i<=$l} {incr i} {
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set x [lindex $list [set p [expr {int(rand()*$l)}]]]
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set list [lreplace $list $p $p]
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set list [linsert $list [expr {int(rand()*$l)}] $x]
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}
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return $list
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}
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# Get the dictionary of nets with one corresponding source wire
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# of a PIP from the todo list
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proc get_nets_with_todo_pip_wires {direction net_regexp wire_regexp used_destinations {verbose false}} {
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set todo_map [load_todo $direction]
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set nets [get_nets]
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set todo_nets [dict create]
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foreach net $nets {
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if {![regexp $net_regexp $net]} {
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continue
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}
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# Check to see if this net is one we are interested in*
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set wires [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTP_COMMON_MID*" && (NAME =~ "*CK_IN*" || NAME =~ "*MUX*")} -quiet]
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set wire_found 0
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foreach wire $wires {
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if [regexp $wire_regexp $wire] {
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set wire_found 1
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break
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}
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}
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if {$wire_found == 0} {
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if {$verbose} {
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puts "$net not going to a GTP common wire, skipping."
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}
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continue
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}
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set tile [lindex [split $wire /] 0]
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set wire [lindex [split $wire /] 1]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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if { ![dict exists $todo_map $wire] } {
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continue
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}
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set candidates [dict get $todo_map $wire]
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# This net is interesting, see if it is already going somewhere we
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# want.
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set found_target 0
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foreach other_wire $wires {
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if { $found_target == 1 } {
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break
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}
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set other_wire [lindex [split $other_wire /] 1]
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if { $wire == $other_wire } {
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continue
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}
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foreach candidate $candidates {
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set candidate_tile_type [lindex $candidate 0]
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if {$candidate_tile_type != $tile_type} {
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continue
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}
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set candidate_wire [lindex $candidate 1]
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if { $other_wire == $candidate } {
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set found_target 1
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if {$verbose} {
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puts "Interesting net $net already going from $wire to $other_wire."
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}
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set_property IS_ROUTE_FIXED 1 $net
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dict set used_destinations "$tile/$candidate_wire" 1
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break
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}
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}
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}
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if { $found_target == 1 } {
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# Net already has an interesting feature - don't reroute.
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continue
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}
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dict set todo_nets $net [list $tile $wire]
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if {$verbose} {
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puts "Interesting net $net (including $wire) is being rerouted."
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}
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}
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return $todo_nets
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}
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proc remove_net_randomly {wire_regexp} {
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# Randomly removes a net containing a given wire
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set nets [get_nets]
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set net_to_remove ""
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foreach net $nets {
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set wires [get_wires -of_objects $net]
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foreach wire $wires {
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if [regexp $wire_regexp $wire] {
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set net_to_remove $net
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break
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}
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}
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}
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if { $net_to_remove != "" && rand() <= 0.1 } {
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puts "Removing net: $net_to_remove"
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remove_net $net_to_remove
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}
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}
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proc route_todo {} {
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# It is very common to have nets passing through the
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# HCLK_GTP_CK_IN[01] wires, resulting in <const1> results.
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# This step removes the net containing the problematic
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# wire with a 10% probability
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remove_net_randomly "HCLK_GTP_CK_IN0"
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remove_net_randomly "HCLK_GTP_CK_IN1"
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set used_destinations [dict create]
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set todo_map [load_todo "dsts"]
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set gtp_channel_nets [get_nets_with_todo_pip_wires "dsts" "gtp_channel_clock" "GTPE2_COMMON_\[TR\]XOUTCLK_MUX_\[0123\]" $used_destinations true]
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set ibufds_nets [get_nets_with_todo_pip_wires "dsts" "ibufds_clock" "IBUFDS_GTPE2_\[01\]_MGTCLKOUT_MUX" $used_destinations true]
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set gtp_nets [dict merge $gtp_channel_nets $ibufds_nets]
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puts "GTP nets: $gtp_nets"
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dict for {net tile_wire} $gtp_nets {
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set tile [lindex $tile_wire 0]
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set wire [lindex $tile_wire 1]
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set dsts [dict get $todo_map $wire]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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set todos {}
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set old_origin_wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTP_COMMON_MID_LEFT*" && NAME =~ "*HCLK_GTP_CK_IN*"}]
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if {$old_origin_wire == {}} {
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continue
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}
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puts "Rerouting net $net at $tile / $wire (type $tile_type)"
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puts "Previous target wire: $old_origin_wire"
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set old_origin_node [get_nodes -of_objects $old_origin_wire]
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foreach dst $dsts {
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set dst_wire [lindex $dst 1]
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lappend todos $dst_wire
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}
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set todos_length [llength $todos]
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if {$todos_length == 0} {
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continue
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}
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puts "All todos for $tile_type / $wire"
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foreach dst_wire $todos {
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puts " - $dst_wire"
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}
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set todos [shuffle_list $todos]
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set target_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
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puts "Target node: $target_node"
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route_design -unroute -nets $net
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# Find an output in the todo list that can drive.
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foreach dst_wire $todos {
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if { [dict exists $used_destinations "$tile/$dst_wire"] } {
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puts "Not routing to $tile / $dst_wire, in use."
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continue
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}
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set origin_wire [get_wires "$tile/$dst_wire"]
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set origin_node [get_nodes -of_objects $origin_wire]
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if {[llength $origin_node] == 0} {
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error "Failed to find node for $tile/$dst_wire."
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}
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set old_net [get_nets -of_objects $origin_node -quiet]
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if {$old_net != {}} {
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puts "Unrouting the old net: $old_net"
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route_design -unroute -nets $old_net
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}
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# Route the net through the desired node
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puts "Attempting to route to $dst_wire for net $net."
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set route_status [route_via $net [list $origin_node] 0]
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if {$route_status == 0} {
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puts "WARNING: route failed, continue with next todo"
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continue
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}
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puts "Target node: $target_node"
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puts "Origin wire: $origin_wire, Old origin wire: $old_origin_wire"
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puts "Origin node: $origin_node, Old origin node: $old_origin_node"
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dict set used_destinations "$origin_wire" 1
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break
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}
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}
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set todo_map [load_todo "srcs"]
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set pll_nets [get_nets_with_todo_pip_wires "srcs" "pll_clock" "HCLK_GTP_CK_IN" $used_destinations true]
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set mmcm_nets [get_nets_with_todo_pip_wires "srcs" "mmcm_clock" "HCLK_GTP_CK_IN" $used_destinations true]
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set cmt_nets [dict merge $pll_nets $mmcm_nets]
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puts "CMT nets: $cmt_nets"
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dict for {net tile_wire} $cmt_nets {
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set tile [lindex $tile_wire 0]
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set wire [lindex $tile_wire 1]
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set dsts [dict keys $todo_map]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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set todos {}
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set old_origin_dst_wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTP_COMMON_MID*"}]
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if {$old_origin_dst_wire == {}} {
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continue
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}
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puts "Rerouting net $net at $tile / $wire (type $tile_type)"
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puts "Previous target wire: $old_origin_dst_wire"
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set old_origin_node [get_nodes -of_objects $old_origin_dst_wire]
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if [regexp "HCLK_GTP_CK_IN.*" $old_origin_dst_wire match group] {
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set old_target_side $group
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}
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foreach dst $dsts {
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set srcs [dict get $todo_map $dst]
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foreach src $srcs {
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set src_wire [lindex $src 1]
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set is_gtp_net 1
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if [regexp "HCLK_GTP_CK_MUX.*" $src_wire match group] {
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set is_gtp_net 0
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}
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if {$is_gtp_net == 1} {
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continue
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}
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set wire_pairs [list $src_wire $dst]
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lappend todos $wire_pairs
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}
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}
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set todos_length [llength $todos]
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if {$todos_length == 0} {
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continue
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}
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puts "All todos for $tile_type / $wire"
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foreach src_wire $todos {
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puts " - $src_wire"
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}
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set todos [shuffle_list $todos]
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set target_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
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puts "Target node: $target_node"
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route_design -unroute -nets $net
|
||||
|
||||
# Find an output in the todo list that can drive.
|
||||
foreach wire_pair $todos {
|
||||
|
||||
set src_wire [lindex $wire_pair 0]
|
||||
set dst_wire [lindex $wire_pair 1]
|
||||
|
||||
if { [dict exists $used_destinations "$tile/$dst_wire"] } {
|
||||
puts "Not routing to $tile / $dst_wire, in use."
|
||||
continue
|
||||
}
|
||||
|
||||
if { [dict exists $used_destinations "$tile/$src_wire"] } {
|
||||
puts "Not routing to $tile / $src_wire, in use."
|
||||
continue
|
||||
}
|
||||
|
||||
set origin_src_wire [get_wires "$tile/$src_wire"]
|
||||
set origin_src_node [get_nodes -of_objects $origin_src_wire]
|
||||
if {[llength $origin_src_node] == 0} {
|
||||
error "Failed to find node for $tile/$src_wire."
|
||||
}
|
||||
|
||||
set origin_dst_wire [get_wires "$tile/$dst_wire"]
|
||||
set origin_dst_node [get_nodes -of_objects $origin_dst_wire]
|
||||
if {[llength $origin_dst_node] == 0} {
|
||||
error "Failed to find node for $tile/$dst_wire."
|
||||
}
|
||||
|
||||
set old_src_net [get_nets -of_objects $origin_src_node -quiet]
|
||||
if {$old_src_net != {}} {
|
||||
puts "Unrouting the old net: $old_src_net"
|
||||
route_design -unroute -nets $old_src_net
|
||||
}
|
||||
|
||||
set old_dst_net [get_nets -of_objects $origin_dst_node -quiet]
|
||||
if {$old_dst_net != {}} {
|
||||
puts "Unrouting the old net: $old_dst_net"
|
||||
route_design -unroute -nets $old_dst_net
|
||||
}
|
||||
|
||||
# Route the net through the desired node
|
||||
puts "Attempting to route to $src_wire and $dst_wire for net $net."
|
||||
set route_status [route_via $net [list $origin_src_node $origin_dst_node]]
|
||||
|
||||
puts "Target node: $target_node"
|
||||
puts "Origin src wire: $origin_src_wire"
|
||||
puts "Origin src node: $origin_src_node"
|
||||
puts "Origin dst wire: $origin_dst_wire"
|
||||
puts "Origin dst node: $origin_dst_node"
|
||||
|
||||
dict set used_destinations "$origin_dst_wire" 1
|
||||
dict set used_destinations "$origin_src_wire" 1
|
||||
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-38}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1575}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1684}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-1712}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDIL-1}]
|
||||
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
|
||||
|
||||
place_design -directive Quick
|
||||
route_design -directive Quick
|
||||
route_todo
|
||||
route_design
|
||||
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_pip_txtdata design.txt
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
# Copyright (C) 2017-2020 The Project X-Ray Authors
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
proc print_tile_pips {tile_type filename} {
|
||||
set fp [open $filename w]
|
||||
set pips [dict create]
|
||||
foreach tile [get_tiles -filter "TYPE == $tile_type"] {
|
||||
foreach pip [lsort [get_pips -of_objects $tile]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
|
||||
# Skip pips with disconnected nodes
|
||||
set src_node [get_nodes -of_objects $src]
|
||||
|
||||
if { $src_node == {} } {
|
||||
continue
|
||||
}
|
||||
|
||||
set dst_node [get_nodes -of_objects $dst]
|
||||
if { $dst_node == {} } {
|
||||
continue
|
||||
}
|
||||
|
||||
set dst_wire [regsub {.*/} $dst ""]
|
||||
set dst_hclk_match [regexp {HCLK_GTP_CK_IN[0-9]+} $dst_wire]
|
||||
set dst_ibufds_mux_match [regexp {IBUFDS_GTPE2_[01]_MGTCLKOUT_MUX} $dst_wire]
|
||||
set dst_gtp_mux_match [regexp {GTPE2_COMMON_[RT]XOUTCLK_MUX_[0123]} $dst_wire]
|
||||
|
||||
if { $dst_hclk_match || $dst_ibufds_mux_match || $dst_gtp_mux_match } {
|
||||
set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
if ![dict exists $pips $pip_string] {
|
||||
puts $fp $pip_string
|
||||
dict set pips $pip_string 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
set_property design_mode PinPlanning [current_fileset]
|
||||
open_io_design -name io_1
|
||||
|
||||
print_tile_pips GTP_COMMON_MID_LEFT gtp_common.txt
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (C) 2017-2020 The Project X-Ray Authors
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
set_property design_mode PinPlanning [current_fileset]
|
||||
open_io_design -name io_1
|
||||
|
||||
set fp [open "cmt_regions.csv" "w"]
|
||||
foreach site_type {MMCME2_ADV IBUFDS_GTE2 GTPE2_CHANNEL GTPE2_COMMON PLLE2_ADV BUFHCE} {
|
||||
foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
|
||||
puts $fp "$site,[get_property CLOCK_REGION $site]"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2017-2020 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
import os
|
||||
import random
|
||||
import math
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray import verilog
|
||||
from prjxray import lut_maker
|
||||
from prjxray.db import Database
|
||||
|
||||
|
||||
def read_site_to_cmt():
|
||||
""" Yields clock sources and which CMT they route within. """
|
||||
with open(os.path.join(os.getenv('FUZDIR'), 'build',
|
||||
'cmt_regions.csv')) as f:
|
||||
for l in f:
|
||||
site, cmt = l.strip().split(',')
|
||||
yield (site, cmt)
|
||||
|
||||
|
||||
class ClockSources(object):
|
||||
""" Class for tracking clock sources.
|
||||
"""
|
||||
|
||||
def __init__(self, limit=14):
|
||||
self.sources = {}
|
||||
self.source_to_cmt = {}
|
||||
self.used_sources_from_cmt = {}
|
||||
self.limit = limit
|
||||
|
||||
def add_clock_source(self, source, cmt):
|
||||
""" Adds a source from a specific CMT.
|
||||
|
||||
"""
|
||||
if cmt not in self.sources:
|
||||
self.sources[cmt] = []
|
||||
|
||||
self.sources[cmt].append(source)
|
||||
self.source_to_cmt[source] = cmt
|
||||
|
||||
def sources_depleted(self, cmt):
|
||||
if cmt in self.sources:
|
||||
if cmt not in self.used_sources_from_cmt:
|
||||
return False
|
||||
|
||||
return self.sources[cmt] == self.used_sources_from_cmt[cmt]
|
||||
|
||||
return True
|
||||
|
||||
def get_random_source(self, cmt, no_repeats=True):
|
||||
""" Get a random source that is routable to the specific CMT.
|
||||
|
||||
get_random_source will return a source that is either cmt='ANY',
|
||||
cmt equal to the input CMT, or the adjecent CMT.
|
||||
|
||||
"""
|
||||
|
||||
choices = []
|
||||
|
||||
if cmt in self.sources:
|
||||
choices.extend(self.sources[cmt])
|
||||
|
||||
random.shuffle(choices)
|
||||
for source in choices:
|
||||
|
||||
source_cmt = self.source_to_cmt[source]
|
||||
|
||||
if source_cmt not in self.used_sources_from_cmt:
|
||||
self.used_sources_from_cmt[source_cmt] = set()
|
||||
|
||||
if no_repeats and source in self.used_sources_from_cmt[source_cmt]:
|
||||
continue
|
||||
|
||||
if len(self.used_sources_from_cmt[source_cmt]) >= self.limit:
|
||||
continue
|
||||
|
||||
self.used_sources_from_cmt[source_cmt].add(source)
|
||||
return source
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def print_bufhce(name, net):
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
BUFHCE {site} (
|
||||
.I({clock})
|
||||
);""".format(site=name, clock=net))
|
||||
|
||||
|
||||
def main():
|
||||
"""
|
||||
GTP_COMMON_MID has clock pips from:
|
||||
|
||||
2 IBUFDS_GTE2 sites (within the GTP_CMMON tile)
|
||||
4 GTP_CHANNEL sites within the same column. Each GTP_CHANNEL can provide 2 clocks
|
||||
14 clocks lines from the HROW spine
|
||||
"""
|
||||
|
||||
cmt_clock_sources = ClockSources()
|
||||
gtp_channel_clock_sources = ClockSources()
|
||||
ibufds_clock_sources = ClockSources()
|
||||
site_to_cmt = dict(read_site_to_cmt())
|
||||
clock_region_limit = dict()
|
||||
clock_region_serdes_location = dict()
|
||||
|
||||
db = Database(util.get_db_root(), util.get_part())
|
||||
grid = db.grid()
|
||||
|
||||
def gen_sites(desired_site_type):
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == desired_site_type:
|
||||
yield tile_name, site
|
||||
|
||||
clock_region_sites = set()
|
||||
|
||||
def get_clock_region_site(site_type, clk_reg):
|
||||
for site_name, reg in site_to_cmt.items():
|
||||
if site_name.startswith(site_type) and reg in clk_reg:
|
||||
if site_name not in clock_region_sites:
|
||||
clock_region_sites.add(site_name)
|
||||
return site_name
|
||||
|
||||
cmt_with_gtp = set()
|
||||
for tile_name, site in gen_sites('GTPE2_COMMON'):
|
||||
cmt_with_gtp.add(site_to_cmt[site])
|
||||
|
||||
ibufds_inputs = dict()
|
||||
input_wires = list()
|
||||
for _, site in gen_sites('IBUFDS_GTE2'):
|
||||
if site_to_cmt[site] not in cmt_with_gtp:
|
||||
continue
|
||||
|
||||
ibufds_i = "{}_ibufds_i".format(site)
|
||||
ibufds_ib = "{}_ibufds_ib".format(site)
|
||||
ibufds_inputs[site] = [ibufds_i, ibufds_ib]
|
||||
|
||||
input_wires.append("input wire {}".format(ibufds_i))
|
||||
input_wires.append("input wire {}".format(ibufds_ib))
|
||||
|
||||
print(
|
||||
'''
|
||||
module top(
|
||||
{}
|
||||
);
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy();
|
||||
'''.format(",\n\t".join(input_wires)))
|
||||
|
||||
for _, site in gen_sites('MMCME2_ADV'):
|
||||
if site_to_cmt[site] not in cmt_with_gtp:
|
||||
continue
|
||||
|
||||
mmcm_clocks = [
|
||||
'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
|
||||
for idx in range(7)
|
||||
]
|
||||
|
||||
for clk in mmcm_clocks:
|
||||
cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
|
||||
|
||||
print(
|
||||
"""
|
||||
wire cin1_{site}, cin2_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
MMCME2_ADV pll_{site} (
|
||||
.CLKIN1(cin1_{site}),
|
||||
.CLKIN2(cin2_{site}),
|
||||
.CLKOUT0({c0}),
|
||||
.CLKOUT1({c1}),
|
||||
.CLKOUT2({c2}),
|
||||
.CLKOUT3({c3}),
|
||||
.CLKOUT4({c4}),
|
||||
.CLKOUT5({c5}),
|
||||
.CLKOUT6({c6})
|
||||
);""".format(
|
||||
site=site,
|
||||
c0=mmcm_clocks[0],
|
||||
c1=mmcm_clocks[1],
|
||||
c2=mmcm_clocks[2],
|
||||
c3=mmcm_clocks[3],
|
||||
c4=mmcm_clocks[4],
|
||||
c5=mmcm_clocks[5],
|
||||
c6=mmcm_clocks[6]))
|
||||
|
||||
for _, site in gen_sites('PLLE2_ADV'):
|
||||
if site_to_cmt[site] not in cmt_with_gtp:
|
||||
continue
|
||||
|
||||
pll_clocks = [
|
||||
'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
|
||||
for idx in range(7)
|
||||
]
|
||||
|
||||
for clk in pll_clocks:
|
||||
cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
|
||||
|
||||
print(
|
||||
"""
|
||||
wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5}, {c6};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
PLLE2_ADV pll_{site} (
|
||||
.CLKIN1(cin1_{site}),
|
||||
.CLKIN2(cin2_{site}),
|
||||
.CLKFBIN(clkfbin_{site}),
|
||||
.CLKOUT0({c0}),
|
||||
.CLKOUT1({c1}),
|
||||
.CLKOUT2({c2}),
|
||||
.CLKOUT3({c3}),
|
||||
.CLKOUT4({c4}),
|
||||
.CLKOUT5({c5}),
|
||||
.CLKFBOUT({c6})
|
||||
);""".format(
|
||||
site=site,
|
||||
c0=pll_clocks[0],
|
||||
c1=pll_clocks[1],
|
||||
c2=pll_clocks[2],
|
||||
c3=pll_clocks[3],
|
||||
c4=pll_clocks[4],
|
||||
c5=pll_clocks[5],
|
||||
c6=pll_clocks[6],
|
||||
))
|
||||
|
||||
for tile, site in gen_sites('IBUFDS_GTE2'):
|
||||
if site_to_cmt[site] not in cmt_with_gtp:
|
||||
continue
|
||||
|
||||
ibufds_clock = 'ibufds_clock_{site}'.format(site=site)
|
||||
|
||||
ibufds_clock_sources.add_clock_source(ibufds_clock, site_to_cmt[site])
|
||||
|
||||
out_port = "O" if random.random() < 0.5 else "ODIV2"
|
||||
i_port = ibufds_inputs[site][0]
|
||||
ib_port = ibufds_inputs[site][1]
|
||||
|
||||
print(
|
||||
"""
|
||||
wire {o};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
IBUFDS_GTE2 ibufds_{site} (
|
||||
.I({i}),
|
||||
.IB({ib}),
|
||||
.{out_port}({o})
|
||||
);""".format(
|
||||
site=site,
|
||||
i=i_port,
|
||||
ib=ib_port,
|
||||
o=ibufds_clock,
|
||||
out_port=out_port))
|
||||
|
||||
for _, site in gen_sites('GTPE2_CHANNEL'):
|
||||
if site_to_cmt[site] not in cmt_with_gtp:
|
||||
continue
|
||||
|
||||
gtp_channel_clock_rx = 'gtp_channel_clock_{site}_rxclkout'.format(
|
||||
site=site)
|
||||
gtp_channel_clock_tx = 'gtp_channel_clock_{site}_txclkout'.format(
|
||||
site=site)
|
||||
|
||||
gtp_channel_clock_sources.add_clock_source(
|
||||
gtp_channel_clock_rx, site_to_cmt[site])
|
||||
gtp_channel_clock_sources.add_clock_source(
|
||||
gtp_channel_clock_tx, site_to_cmt[site])
|
||||
|
||||
print(
|
||||
"""
|
||||
wire {rx}, {tx};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
GTPE2_CHANNEL gtp_channel_{site} (
|
||||
.RXOUTCLK({rx}),
|
||||
.TXOUTCLK({tx})
|
||||
);""".format(site=site, rx=gtp_channel_clock_rx, tx=gtp_channel_clock_tx))
|
||||
|
||||
for cmt in cmt_with_gtp:
|
||||
cmt_clock_used = 0
|
||||
|
||||
for _, bufhce in gen_sites('BUFHCE'):
|
||||
if site_to_cmt[bufhce] != cmt:
|
||||
continue
|
||||
|
||||
chance = random.random()
|
||||
|
||||
if chance < 0.2 or cmt_clock_used < 3:
|
||||
cmt_clock_used += 1
|
||||
clock_name = cmt_clock_sources.get_random_source(cmt)
|
||||
elif chance > 0.2 and chance < 0.4:
|
||||
clock_name = ibufds_clock_sources.get_random_source(cmt)
|
||||
elif chance < 0.6:
|
||||
clock_name = gtp_channel_clock_sources.get_random_source(cmt)
|
||||
else:
|
||||
continue
|
||||
|
||||
if clock_name is None:
|
||||
continue
|
||||
|
||||
print_bufhce("{}".format(bufhce), clock_name)
|
||||
|
||||
print('endmodule')
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -377,6 +377,8 @@ class Segmaker:
|
|||
tile_type_norm = 'CMT_LOWER_B'
|
||||
if 'GTP_CHANNEL' in tile_type_norm:
|
||||
tile_type_norm = 'GTP_CHANNEL'
|
||||
if 'GTP_COMMON' in tile_type_norm:
|
||||
tile_type_norm = 'GTP_COMMON'
|
||||
|
||||
# ignore dummy tiles (ex: VBRK)
|
||||
if len(tiledata['bits']) == 0:
|
||||
|
|
|
|||
|
|
@ -164,10 +164,10 @@ case "$1" in
|
|||
cp "$2" "$tmp1" ;;
|
||||
|
||||
gtp_common_mid_left)
|
||||
sed < "$2" > "$tmp1" -e 's/^GTP_COMMON_MID_RIGHT\./GTP_COMMON_MID_LEFT./' ;;
|
||||
sed < "$2" > "$tmp1" -e 's/^GTP_COMMON\./GTP_COMMON_MID_LEFT./' ;;
|
||||
|
||||
gtp_common_mid_right)
|
||||
cp "$2" "$tmp1" ;;
|
||||
sed < "$2" > "$tmp1" -e 's/^GTP_COMMON\./GTP_COMMON_MID_RIGHT./' ;;
|
||||
|
||||
gtp_channel_0)
|
||||
sed < "$2" > "$tmp1" -e 's/^GTP_CHANNEL\./GTP_CHANNEL_0./' ;;
|
||||
|
|
|
|||
Loading…
Reference in New Issue