mirror of https://github.com/openXC7/prjxray.git
Update "simple" fuzzer
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
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@ -12,3 +12,4 @@
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/usage_statistics_webtalk.*
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/lutlist.txt
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/segdata.txt
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/database.txt
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@ -1,9 +1,9 @@
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module top(input clk, din, stb, output dout);
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reg [33:0] din_bits;
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wire [70:0] dout_bits;
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reg [39:0] din_bits;
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wire [76:0] dout_bits;
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reg [33:0] din_shr;
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reg [70:0] dout_shr;
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reg [39:0] din_shr;
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reg [76:0] dout_shr;
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always @(posedge clk) begin
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if (stb) begin
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@ -11,12 +11,20 @@ module top(input clk, din, stb, output dout);
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dout_shr <= dout_bits;
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end else begin
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din_shr <= {din_shr, din};
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dout_shr <= {dout_shr, din_shr[33]};
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dout_shr <= {dout_shr, din_shr[39]};
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end
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end
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assign dout = dout_shr[70];
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assign dout = dout_shr[76];
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stuff stuff (
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.clk(clk),
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.din_bits(din_bits),
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.dout_bits(dout_bits)
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);
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endmodule
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module stuff(input clk, input [39:0] din_bits, output [76:0] dout_bits);
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picorv32 picorv32 (
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.clk(clk),
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.resetn(din_bits[0]),
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@ -28,4 +36,53 @@ module top(input clk, din, stb, output dout);
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.mem_wstrb(dout_bits[70:67]),
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.mem_rdata(din_bits[33:2])
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);
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randluts randluts (
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.din(din_bits[39:34]),
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.dout(dout_bits[76:71])
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);
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endmodule
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module randluts(input [5:0] din, output [5:0] dout);
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localparam integer N = 300;
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function [31:0] xorshift32(input [31:0] xorin);
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begin
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xorshift32 = xorin;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [63:0] lutinit(input [7:0] a, b);
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begin
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lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b}))));
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lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a}))));
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end
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endfunction
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wire [(N+1)*6-1:0] nets;
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assign nets[5:0] = din;
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assign dout = nets[(N+1)*6-1:N*6];
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genvar i, j;
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generate
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for (i = 0; i < N; i = i+1) begin:is
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for (j = 0; j < 6; j = j+1) begin:js
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LUT6 #(
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.INIT(lutinit(i, j))
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) lut (
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.I0(nets[6*i+0]),
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.I1(nets[6*i+1]),
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.I2(nets[6*i+2]),
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.I3(nets[6*i+3]),
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.I4(nets[6*i+4]),
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.I5(nets[6*i+5]),
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.O(nets[6*i+6+j])
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);
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end
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end
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endgenerate
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endmodule
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@ -14,11 +14,11 @@ set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells picorv32]
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add_cells_to_pblock [get_pblocks roi] [get_cells stuff]
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resize_pblock [get_pblocks roi] -add {$XRAY_ROI}
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# requires partial reconfiguration license
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set_property HD.RECONFIGURABLE TRUE [get_cells picorv32]
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set_property HD.RECONFIGURABLE TRUE [get_cells stuff]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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@ -42,9 +42,8 @@ write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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puts "Writing lutlist.txt."
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current_instance picorv32
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set fp [open "lutlist.txt" w]
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set luts [get_cells -filter {REF_NAME == LUT6}]
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set luts [get_cells -hierarchical -filter {REF_NAME == LUT6}]
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foreach lut \$luts {
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set bel [get_property BEL \$lut]
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set loc [get_property LOC \$lut]
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@ -64,4 +63,5 @@ else
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fi
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python3 segdata.py
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../tools/segmatch < segdata.txt > database.txt
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@ -79,7 +79,13 @@ for tilename, tiledata in grid["tiles"].items():
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assert 0
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for name, value in luts[site].items():
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segments[segname]["tags"]["%s.%s.%s" % (tiledata["props"]["TYPE"], sitekey, name)] = value
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tile_type = tiledata["props"]["TYPE"]
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# LUT init bits are in the same position for all CLBL[LM]_[LR] tiles
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if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name:
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tile_type = "CLBLX_X"
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segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value
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base_frame = int(tiledata["cfgcol"]["BASE_FRAMEID"][2:], 16)
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for wordidx in tiledata["cfgcol"]["WORDS"]:
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