diff --git a/simple/.gitignore b/simple/.gitignore
index 4b30a3eb..4fbc6e9c 100644
--- a/simple/.gitignore
+++ b/simple/.gitignore
@@ -12,3 +12,4 @@
 /usage_statistics_webtalk.*
 /lutlist.txt
 /segdata.txt
+/database.txt
diff --git a/simple/design.v b/simple/design.v
index 6926ff12..f21866ed 100644
--- a/simple/design.v
+++ b/simple/design.v
@@ -1,9 +1,9 @@
 module top(input clk, din, stb, output dout);
-	reg [33:0] din_bits;
-	wire [70:0] dout_bits;
+	reg [39:0] din_bits;
+	wire [76:0] dout_bits;
 
-	reg [33:0] din_shr;
-	reg [70:0] dout_shr;
+	reg [39:0] din_shr;
+	reg [76:0] dout_shr;
 
 	always @(posedge clk) begin
 		if (stb) begin
@@ -11,12 +11,20 @@ module top(input clk, din, stb, output dout);
 			dout_shr <= dout_bits;
 		end else begin
 			din_shr <= {din_shr, din};
-			dout_shr <= {dout_shr, din_shr[33]};
+			dout_shr <= {dout_shr, din_shr[39]};
 		end
 	end
 
-	assign dout = dout_shr[70];
+	assign dout = dout_shr[76];
 
+	stuff stuff (
+		.clk(clk),
+		.din_bits(din_bits),
+		.dout_bits(dout_bits)
+	);
+endmodule
+
+module stuff(input clk, input [39:0] din_bits, output [76:0] dout_bits);
 	picorv32 picorv32 (
 		.clk(clk),
 		.resetn(din_bits[0]),
@@ -28,4 +36,53 @@ module top(input clk, din, stb, output dout);
 		.mem_wstrb(dout_bits[70:67]),
 		.mem_rdata(din_bits[33:2])
 	);
+
+	randluts randluts (
+		.din(din_bits[39:34]),
+		.dout(dout_bits[76:71])
+	);
+endmodule
+
+module randluts(input [5:0] din, output [5:0] dout);
+	localparam integer N = 300;
+
+	function [31:0] xorshift32(input [31:0] xorin);
+		begin
+			xorshift32 = xorin;
+			xorshift32 = xorshift32 ^ (xorshift32 << 13);
+			xorshift32 = xorshift32 ^ (xorshift32 >> 17);
+			xorshift32 = xorshift32 ^ (xorshift32 <<  5);
+		end
+	endfunction
+
+	function [63:0] lutinit(input [7:0] a, b);
+		begin
+			lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b}))));
+			lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a}))));
+		end
+	endfunction
+
+	wire [(N+1)*6-1:0] nets;
+
+	assign nets[5:0] = din;
+	assign dout = nets[(N+1)*6-1:N*6];
+
+	genvar i, j;
+	generate
+		for (i = 0; i < N; i = i+1) begin:is
+			for (j = 0; j < 6; j = j+1) begin:js
+				LUT6 #(
+					.INIT(lutinit(i, j))
+				) lut (
+					.I0(nets[6*i+0]),
+					.I1(nets[6*i+1]),
+					.I2(nets[6*i+2]),
+					.I3(nets[6*i+3]),
+					.I4(nets[6*i+4]),
+					.I5(nets[6*i+5]),
+					.O(nets[6*i+6+j])
+				);
+			end
+		end
+	endgenerate
 endmodule
diff --git a/simple/runme.sh b/simple/runme.sh
index 2610b0ac..4cafba54 100644
--- a/simple/runme.sh
+++ b/simple/runme.sh
@@ -14,11 +14,11 @@ set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
 		[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
 
 create_pblock roi
-add_cells_to_pblock [get_pblocks roi] [get_cells picorv32]
+add_cells_to_pblock [get_pblocks roi] [get_cells stuff]
 resize_pblock [get_pblocks roi] -add {$XRAY_ROI}
 
 # requires partial reconfiguration license
-set_property HD.RECONFIGURABLE TRUE [get_cells picorv32]
+set_property HD.RECONFIGURABLE TRUE [get_cells stuff]
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
@@ -42,9 +42,8 @@ write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 
 puts "Writing lutlist.txt."
-current_instance picorv32
 set fp [open "lutlist.txt" w]
-set luts [get_cells -filter {REF_NAME == LUT6}]
+set luts [get_cells -hierarchical -filter {REF_NAME == LUT6}]
 foreach lut \$luts {
 	set bel [get_property BEL \$lut]
 	set loc [get_property LOC \$lut]
@@ -64,4 +63,5 @@ else
 fi
 
 python3 segdata.py
+../tools/segmatch < segdata.txt > database.txt
 
diff --git a/simple/segdata.py b/simple/segdata.py
index edccfec5..b5894980 100644
--- a/simple/segdata.py
+++ b/simple/segdata.py
@@ -79,7 +79,13 @@ for tilename, tiledata in grid["tiles"].items():
             assert 0
 
         for name, value in luts[site].items():
-            segments[segname]["tags"]["%s.%s.%s" % (tiledata["props"]["TYPE"], sitekey, name)] = value
+            tile_type = tiledata["props"]["TYPE"]
+
+            # LUT init bits are in the same position for all CLBL[LM]_[LR] tiles
+            if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name:
+                tile_type = "CLBLX_X"
+
+            segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value
 
     base_frame = int(tiledata["cfgcol"]["BASE_FRAMEID"][2:], 16)
     for wordidx in tiledata["cfgcol"]["WORDS"]: