mirror of https://github.com/openXC7/prjxray.git
89 lines
1.8 KiB
Verilog
89 lines
1.8 KiB
Verilog
module top(input clk, din, stb, output dout);
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reg [39:0] din_bits;
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wire [76:0] dout_bits;
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reg [39:0] din_shr;
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reg [76:0] dout_shr;
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always @(posedge clk) begin
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if (stb) begin
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din_bits <= din_shr;
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dout_shr <= dout_bits;
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end else begin
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din_shr <= {din_shr, din};
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dout_shr <= {dout_shr, din_shr[39]};
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end
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end
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assign dout = dout_shr[76];
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stuff stuff (
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.clk(clk),
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.din_bits(din_bits),
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.dout_bits(dout_bits)
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);
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endmodule
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module stuff(input clk, input [39:0] din_bits, output [76:0] dout_bits);
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picorv32 picorv32 (
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.clk(clk),
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.resetn(din_bits[0]),
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.mem_valid(dout_bits[0]),
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.mem_instr(dout_bits[1]),
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.mem_ready(din_bits[1]),
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.mem_addr(dout_bits[33:2]),
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.mem_wdata(dout_bits[66:34]),
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.mem_wstrb(dout_bits[70:67]),
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.mem_rdata(din_bits[33:2])
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);
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randluts randluts (
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.din(din_bits[39:34]),
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.dout(dout_bits[76:71])
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);
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endmodule
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module randluts(input [5:0] din, output [5:0] dout);
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localparam integer N = 300;
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function [31:0] xorshift32(input [31:0] xorin);
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begin
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xorshift32 = xorin;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [63:0] lutinit(input [7:0] a, b);
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begin
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lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b}))));
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lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a}))));
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end
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endfunction
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wire [(N+1)*6-1:0] nets;
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assign nets[5:0] = din;
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assign dout = nets[(N+1)*6-1:N*6];
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genvar i, j;
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generate
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for (i = 0; i < N; i = i+1) begin:is
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for (j = 0; j < 6; j = j+1) begin:js
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LUT6 #(
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.INIT(lutinit(i, j))
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) lut (
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.I0(nets[6*i+0]),
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.I1(nets[6*i+1]),
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.I2(nets[6*i+2]),
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.I3(nets[6*i+3]),
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.I4(nets[6*i+4]),
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.I5(nets[6*i+5]),
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.O(nets[6*i+6+j])
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);
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end
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end
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endgenerate
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endmodule
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