mirror of https://github.com/openXC7/prjxray.git
68 lines
1.8 KiB
Bash
68 lines
1.8 KiB
Bash
#!/bin/bash
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set -ex
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source ../settings.sh
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cat > design.xdc << EOT
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set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports clk]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports din]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports dout]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports stb]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells stuff]
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resize_pblock [get_pblocks roi] -add {$XRAY_ROI}
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# requires partial reconfiguration license
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set_property HD.RECONFIGURABLE TRUE [get_cells stuff]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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EOT
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cat > design.tcl << EOT
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create_project -force -part $XRAY_PART design design
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read_xdc design.xdc
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read_verilog design.v
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read_verilog picorv32.v
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synth_design -top top
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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puts "Writing lutlist.txt."
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set fp [open "lutlist.txt" w]
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set luts [get_cells -hierarchical -filter {REF_NAME == LUT6}]
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foreach lut \$luts {
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set bel [get_property BEL \$lut]
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set loc [get_property LOC \$lut]
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set init [get_property INIT \$lut]
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puts \$fp "\$loc \$bel \$init"
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}
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close \$fp
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EOT
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rm -rf design design.log
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vivado -nojournal -log design.log -mode batch -source design.tcl
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if [ -f design_roi_partial.bit ]; then
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../tools/bitread -o design.bits -zy < design_roi_partial.bit
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else
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../tools/bitread -o design.bits -zy < design.bit
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fi
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python3 segdata.py
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../tools/segmatch < segdata.txt > database.txt
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