From cbbf46112fd3b3e081da172626ca90a73bfe01d6 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Tue, 2 Jul 2019 16:03:02 +0200
Subject: [PATCH] Updated EDIF write to include cell attributes

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 minitests/srl/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile
index c1d730c9..0e465ae7 100644
--- a/minitests/srl/Makefile
+++ b/minitests/srl/Makefile
@@ -30,7 +30,7 @@ $(YOSYS):
 
 ifeq ($(SYNTH), yosys)
 %.edif: %.v $(YOSYS)
-	$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@"  -l $@.log
+	$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@"  -l $@.log
 
 else ifeq ($(SYNTH), vivado)
 %.edif: %.v $(YOSYS)