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virtex7: 035a-iob18-idelay/odelay — L/R-side sort + ODELAY VAR_LOAD DRC 

Two unrelated fixes the HP-IOB18 fuzzers need on a full-chip part:

1) top.py for both idelay and odelay collects all IOB18 tiles
   ('IOB18' in tile_name) but sorted with a key hardcoded to prefix
   'RIOB18_' via create_xy_fun('RIOB18_'), which asserts on the first
   LIOB18_* tile. kintex7's ROI only ever exposed the R side so this
   was latent. Switch to a regex prefix '[LR]IOB18_' (matches the
   existing '\\S+' idiom used by 037-iob18-pips). Doesn't change
   which tiles get collected, so no-op for kintex7.

2) odelay generate.tcl: Vivado 2020.1 enforces DRC REQP-135 (ODELAY
   VAR_LOAD/VAR_LOAD_PIPE requires CNTVALUEIN[0:4] connected) before
   write_bitstream, but the fuzzer intentionally leaves CNTVALUEIN
   unconnected. The idelay generate.tcl already disables IDELAY's
   equivalents (REQP-79/81/84/85/87); add REQP-135 to the odelay
   disable list to mirror.

Verified: idelay/odelay both run to completion on xc7vx485tffg1761-2,
producing valid segdata.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Dr Jonathan Richard Robert Kimmitt 2026-05-27 14:27:08 +01:00
parent 1ebe6937e0
commit 48e7996581
3 changed files with 10 additions and 2 deletions
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4
fuzzers/035a-iob18-idelay/top.py
View File

@ -31,7 +31,9 @@ def gen_sites():
continue
tile_list.append(tile_name)
get_xy = util.create_xy_fun('RIOB18_')
# Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
# the R side), so match either prefix when extracting the (X,Y) sort key.
get_xy = util.create_xy_fun('[LR]IOB18_')
tile_list.sort(key=get_xy)
for iob_tile_name in tile_list:

4
fuzzers/035a-iob18-odelay/generate.tcl
View File

@ -22,6 +22,10 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
# ODELAY VAR_LOAD/VAR_LOAD_PIPE leaves CNTVALUEIN intentionally unconnected for
# fuzzing; Vivado 2020.1 enforces this via REQP-135 (the IDELAY equivalents
# REQP-79/81/.. are already disabled above, which is why the idelay fuzzer passes).
set_property IS_ENABLED 0 [get_drc_checks {REQP-135}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
place_design

4
fuzzers/035a-iob18-odelay/top.py
View File

@ -31,7 +31,9 @@ def gen_sites():
continue
tile_list.append(tile_name)
get_xy = util.create_xy_fun('RIOB18_')
# Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
# the R side), so match either prefix when extracting the (X,Y) sort key.
get_xy = util.create_xy_fun('[LR]IOB18_')
tile_list.sort(key=get_xy)
for iob_tile_name in tile_list: