diff --git a/fuzzers/035a-iob18-idelay/top.py b/fuzzers/035a-iob18-idelay/top.py
index 3c481301..04d5412a 100644
--- a/fuzzers/035a-iob18-idelay/top.py
+++ b/fuzzers/035a-iob18-idelay/top.py
@@ -31,7 +31,9 @@ def gen_sites():
             continue
         tile_list.append(tile_name)
 
-    get_xy = util.create_xy_fun('RIOB18_')
+    # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
+    # the R side), so match either prefix when extracting the (X,Y) sort key.
+    get_xy = util.create_xy_fun('[LR]IOB18_')
     tile_list.sort(key=get_xy)
 
     for iob_tile_name in tile_list:
diff --git a/fuzzers/035a-iob18-odelay/generate.tcl b/fuzzers/035a-iob18-odelay/generate.tcl
index 0ab7b32d..d24aacec 100644
--- a/fuzzers/035a-iob18-odelay/generate.tcl
+++ b/fuzzers/035a-iob18-odelay/generate.tcl
@@ -22,6 +22,10 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
+# ODELAY VAR_LOAD/VAR_LOAD_PIPE leaves CNTVALUEIN intentionally unconnected for
+# fuzzing; Vivado 2020.1 enforces this via REQP-135 (the IDELAY equivalents
+# REQP-79/81/.. are already disabled above, which is why the idelay fuzzer passes).
+set_property IS_ENABLED 0 [get_drc_checks {REQP-135}]
 set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
 
 place_design
diff --git a/fuzzers/035a-iob18-odelay/top.py b/fuzzers/035a-iob18-odelay/top.py
index 7e3db78e..8ca89c7b 100644
--- a/fuzzers/035a-iob18-odelay/top.py
+++ b/fuzzers/035a-iob18-odelay/top.py
@@ -31,7 +31,9 @@ def gen_sites():
             continue
         tile_list.append(tile_name)
 
-    get_xy = util.create_xy_fun('RIOB18_')
+    # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had
+    # the R side), so match either prefix when extracting the (X,Y) sort key.
+    get_xy = util.create_xy_fun('[LR]IOB18_')
     tile_list.sort(key=get_xy)
 
     for iob_tile_name in tile_list: