From 48e79965815165b0a9d82d66298dbc140cbc8ef8 Mon Sep 17 00:00:00 2001 From: Dr Jonathan Richard Robert Kimmitt Date: Wed, 27 May 2026 14:27:08 +0100 Subject: [PATCH] =?UTF-8?q?virtex7:=20035a-iob18-idelay/odelay=20=E2=80=94?= =?UTF-8?q?=20L/R-side=20sort=20+=20ODELAY=20VAR=5FLOAD=20DRC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Two unrelated fixes the HP-IOB18 fuzzers need on a full-chip part: 1) top.py for both idelay and odelay collects all IOB18 tiles ('IOB18' in tile_name) but sorted with a key hardcoded to prefix 'RIOB18_' via create_xy_fun('RIOB18_'), which asserts on the first LIOB18_* tile. kintex7's ROI only ever exposed the R side so this was latent. Switch to a regex prefix '[LR]IOB18_' (matches the existing '\\S+' idiom used by 037-iob18-pips). Doesn't change which tiles get collected, so no-op for kintex7. 2) odelay generate.tcl: Vivado 2020.1 enforces DRC REQP-135 (ODELAY VAR_LOAD/VAR_LOAD_PIPE requires CNTVALUEIN[0:4] connected) before write_bitstream, but the fuzzer intentionally leaves CNTVALUEIN unconnected. The idelay generate.tcl already disables IDELAY's equivalents (REQP-79/81/84/85/87); add REQP-135 to the odelay disable list to mirror. Verified: idelay/odelay both run to completion on xc7vx485tffg1761-2, producing valid segdata. Co-Authored-By: Claude Opus 4.7 --- fuzzers/035a-iob18-idelay/top.py | 4 +++- fuzzers/035a-iob18-odelay/generate.tcl | 4 ++++ fuzzers/035a-iob18-odelay/top.py | 4 +++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/fuzzers/035a-iob18-idelay/top.py b/fuzzers/035a-iob18-idelay/top.py index 3c481301..04d5412a 100644 --- a/fuzzers/035a-iob18-idelay/top.py +++ b/fuzzers/035a-iob18-idelay/top.py @@ -31,7 +31,9 @@ def gen_sites(): continue tile_list.append(tile_name) - get_xy = util.create_xy_fun('RIOB18_') + # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had + # the R side), so match either prefix when extracting the (X,Y) sort key. + get_xy = util.create_xy_fun('[LR]IOB18_') tile_list.sort(key=get_xy) for iob_tile_name in tile_list: diff --git a/fuzzers/035a-iob18-odelay/generate.tcl b/fuzzers/035a-iob18-odelay/generate.tcl index 0ab7b32d..d24aacec 100644 --- a/fuzzers/035a-iob18-odelay/generate.tcl +++ b/fuzzers/035a-iob18-odelay/generate.tcl @@ -22,6 +22,10 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-84}] set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] set_property IS_ENABLED 0 [get_drc_checks {REQP-87}] set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] +# ODELAY VAR_LOAD/VAR_LOAD_PIPE leaves CNTVALUEIN intentionally unconnected for +# fuzzing; Vivado 2020.1 enforces this via REQP-135 (the IDELAY equivalents +# REQP-79/81/.. are already disabled above, which is why the idelay fuzzer passes). +set_property IS_ENABLED 0 [get_drc_checks {REQP-135}] set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}] place_design diff --git a/fuzzers/035a-iob18-odelay/top.py b/fuzzers/035a-iob18-odelay/top.py index 7e3db78e..8ca89c7b 100644 --- a/fuzzers/035a-iob18-odelay/top.py +++ b/fuzzers/035a-iob18-odelay/top.py @@ -31,7 +31,9 @@ def gen_sites(): continue tile_list.append(tile_name) - get_xy = util.create_xy_fun('RIOB18_') + # Virtex-7 exposes both L- and R-side IOB18 tiles (kintex7's ROI only had + # the R side), so match either prefix when extracting the (X,Y) sort key. + get_xy = util.create_xy_fun('[LR]IOB18_') tile_list.sort(key=get_xy) for iob_tile_name in tile_list: