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Some WIP hacks to get virtex running. Will break other families. For now.

This commit is contained in:
Hans Baier 2023-01-11 05:11:43 +00:00
parent d756999cf0
commit 2e1670a760
47 changed files with 187 additions and 157 deletions
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12
Makefile
View File

@ -136,7 +136,7 @@ check-license:
# Targets related to Project X-Ray databases # Targets related to Project X-Ray databases
# ------------------------ # ------------------------
DATABASES=artix7 kintex7 zynq7 spartan7 DATABASES=artix7 kintex7 zynq7 spartan7 virtex7
define database define database
@ -191,8 +191,9 @@ ARTIX_PARTS=artix7_50t artix7_200t
ZYNQ_PARTS=zynq7010 ZYNQ_PARTS=zynq7010
KINTEX_PARTS=kintex7_160t KINTEX_PARTS=kintex7_160t
SPARTAN_PARTS= SPARTAN_PARTS=
VIRTEX_PARTS=
XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} ${VIRTEX_PARTS}
define multiple-parts define multiple-parts
@ -245,6 +246,13 @@ db-extras-kintex7-roi: $(addprefix db-roi-only-,$(KINTEX_PARTS))
db-extras-kintex7-harness: db-extras-kintex7-harness:
@true @true
db-extras-virtex7-parts: $(addprefix db-part-only-,$(VIRTEX_PARTS))
db-extras-virtex7-roi: $(addprefix db-roi-only-,$(VIRTEX_PARTS))
db-extras-virtex7-harness:
@true
db-extras-spartan7-parts: db-extras-spartan7-parts:
@true @true

8
fuzzers/001-part-yaml/generate.tcl
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@ -29,10 +29,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog ../../top.v read_verilog ../../top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

23
fuzzers/005-tilegrid/Makefile
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@ -6,13 +6,31 @@
# #
# SPDX-License-Identifier: ISC # SPDX-License-Identifier: ISC
ifeq (${XRAY_DATABASE}, virtex7)
HAS_HIGH_PERFORMANCE_BANKS = 1
# TODO: some virtex devices have high range banks
HAS_HIGH_RANGE_BANKS = 0
endif
ifeq (${XRAY_DATABASE}, kintex7)
# xc7k420t/xc7k480t have no high performance banks
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
HAS_HIGH_PERFORMANCE_BANKS = 1
else
HAS_HIGH_PERFORMANCE_BANKS = 0
endif
endif
FUZDIR=$(shell pwd) FUZDIR=$(shell pwd)
BUILD_FOLDER=build_${XRAY_PART} BUILD_FOLDER=build_${XRAY_PART}
BUILD_DIR=$(FUZDIR)/$(BUILD_FOLDER) BUILD_DIR=$(FUZDIR)/$(BUILD_FOLDER)
TILEGRID_TDB_DEPENDENCIES= TILEGRID_TDB_DEPENDENCIES=
ifeq (${HAS_HIGH_RANGE_BANKS}, 1)
TILEGRID_TDB_DEPENDENCIES += iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif
TILEGRID_TDB_DEPENDENCIES += monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@ -48,9 +66,7 @@ TILEGRID_TDB_DEPENDENCIES += ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif endif
# Kintex7 only fuzzers # Kintex7 only fuzzers
ifeq (${XRAY_DATABASE}, kintex7) ifeq (${HAS_HIGH_PERFORMANCE_BANKS}, 1)
# xc7k420t/xc7k480t have no high performance banks
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@ -60,7 +76,6 @@ endif
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t)) ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t))
TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif endif
endif
BASICDB_TILEGRID=$(BUILD_FOLDER)/basicdb/${XRAY_FABRIC}/tilegrid.json BASICDB_TILEGRID=$(BUILD_FOLDER)/basicdb/${XRAY_FABRIC}/tilegrid.json

8
fuzzers/005-tilegrid/bram/generate.tcl
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@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/clb/generate.tcl
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@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

4
fuzzers/005-tilegrid/clb_int/generate.tcl
View File

@ -12,8 +12,8 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/mmcm/generate.tcl
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@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/monitor/generate.tcl
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@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/ps7_int/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

18
fuzzers/005-tilegrid/util.tcl
View File

@ -85,7 +85,7 @@ proc make_io_pad_sites {} {
if {[llength $site] == 0} { if {[llength $site] == 0} {
continue continue
} }
if [string match IOB33* [get_property SITE_TYPE $site]] { if [string match IOB18* [get_property SITE_TYPE $site]] {
dict append io_pad_sites $site $pad dict append io_pad_sites $site $pad
} }
} }
@ -114,10 +114,10 @@ proc make_iob_sites {} {
} }
proc assign_iobs_old {} { proc assign_iobs_old {} {
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
} }
proc assign_iobs {} { proc assign_iobs {} {
@ -129,9 +129,9 @@ proc assign_iobs {} {
# Basic pins # Basic pins
# XXX: not all pads are valid, but seems to be working for now # XXX: not all pads are valid, but seems to be working for now
# Maybe better to set to XRAY_PIN_* and take out of the list? # Maybe better to set to XRAY_PIN_* and take out of the list?
set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS18" [get_ports do]
set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS18" [get_ports stb]
# din bus # din bus
set fixed_pins 3 set fixed_pins 3
@ -139,7 +139,7 @@ proc assign_iobs {} {
for {set i 0} {$i < [llength $iports]} {incr i} { for {set i 0} {$i < [llength $iports]} {incr i} {
set pad [lindex $iopad [expr $i+$fixed_pins]] set pad [lindex $iopad [expr $i+$fixed_pins]]
set port [lindex $iports $i] set port [lindex $iports $i]
set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS18" $port
} }
} }

4
fuzzers/007-timing/bel/runme.tcl
View File

@ -13,8 +13,8 @@ proc create_design {} {
read_verilog $::env(SRC_DIR)/top.v read_verilog $::env(SRC_DIR)/top.v
synth_design -top top -flatten_hierarchy none synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

4
fuzzers/007-timing/routing-bels/runme.tcl
View File

@ -13,8 +13,8 @@ proc create_design {} {
read_verilog $::env(SRC_DIR)/top.v read_verilog $::env(SRC_DIR)/top.v
synth_design -top top -flatten_hierarchy none synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/010-clb-lutinit/generate.tcl
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@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog ../../top.v read_verilog ../../top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \ set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical] [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]

8
fuzzers/011-clb-ffconfig/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/012-clb-n5ffmux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/013-clb-ncy0/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/014-clb-ffsrcemux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/015-clb-nffmux/generate.tcl
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@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/016-clb-noutmux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/017-clb-precyinit/generate.tcl
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@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/018-clb-ram/generate.tcl
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@ -10,10 +10,10 @@ proc build {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/019-clb-ndi1mux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/025-bram-config/generate.tcl
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@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/025-bram-config/minitest/runme.tcl
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@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V) read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT) synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/026-bram-data/minitest/runme.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V) read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT) synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/030-iob/minitest/runme.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V) read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT) synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
# set_property roi/dut # set_property roi/dut

10
fuzzers/030-iob/minitest/template.tcl
View File

@ -11,10 +11,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V) read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
@ -27,6 +27,6 @@ route_design
write_checkpoint -force design.dcp write_checkpoint -force design.dcp
# set port [create_port -direction OUT myport] # set port [create_port -direction OUT myport]
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port # set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS18" $port
# set_property PULLTYPE PULLUP $port # set_property PULLTYPE PULLUP $port
# set_property PULLTYPE PULLDOWN $port # set_property PULLTYPE PULLDOWN $port

8
fuzzers/033-mon-xadc/generate.tcl
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@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/038-cfg/generate.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
create_pblock roi create_pblock roi

8
fuzzers/050-pip-seed/generate.tcl
View File

@ -15,10 +15,10 @@ read_verilog $::env(FUZDIR)/picorv32.v
puts "FUZ([pwd]): Synth design" puts "FUZ([pwd]): Synth design"
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
create_pblock roi create_pblock roi
add_cells_to_pblock [get_pblocks roi] [get_cells roi] add_cells_to_pblock [get_pblocks roi] [get_cells roi]

8
fuzzers/051-pip-imuxlout-bypalts/generate.tcl
View File

@ -13,10 +13,10 @@ read_verilog $::env(FUZDIR)/top.v
read_verilog $::env(FUZDIR)/picorv32.v read_verilog $::env(FUZDIR)/picorv32.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/052-pip-clkin/generate.tcl
View File

@ -43,8 +43,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/053-pip-ctrlin/generate.tcl
View File

@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/054-pip-fan-alt/generate.tcl
View File

@ -13,8 +13,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/055-pip-gnd/generate.tcl
View File

@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/056-pip-rem/generate.tcl
View File

@ -25,8 +25,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/057-pip-bi/bipiplist.tcl
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@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) bipiplist bipiplist
read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/057-pip-bi/generate.tcl
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@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/058-pip-hclk/generate.tcl
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@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/059-pip-byp-bounce/generate.tcl
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@ -13,8 +13,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/071-ppips/generate.tcl
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@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v read_verilog $::env(FUZDIR)/top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports a]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports y]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

8
fuzzers/100-dsp-mskpat/generate.tcl
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@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]

19
fuzzers/Makefile
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@ -95,6 +95,13 @@ all:: 005-tilegrid/run.ok
endif endif
ifneq ($(XRAY_DATABASE),kintex7) ifneq ($(XRAY_DATABASE),kintex7)
HAS_HIGH_PERFORMANCE_BANKS = 1
endif
ifneq ($(XRAY_DATABASE),virtex7)
HAS_HIGH_PERFORMANCE_BANKS = 1
endif
ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,007-timing,005-tilegrid,all)) $(eval $(call fuzzer,007-timing,005-tilegrid,all))
endif endif
$(eval $(call fuzzer,010-clb-lutinit,005-tilegrid,all)) $(eval $(call fuzzer,010-clb-lutinit,005-tilegrid,all))
@ -113,29 +120,29 @@ $(eval $(call fuzzer,027-bram36-config,005-tilegrid,all))
$(eval $(call fuzzer,028-fifo-config,005-tilegrid,all)) $(eval $(call fuzzer,028-fifo-config,005-tilegrid,all))
$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid,all)) $(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid,all))
$(eval $(call fuzzer,030-iob,005-tilegrid,all)) $(eval $(call fuzzer,030-iob,005-tilegrid,all))
ifeq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,030-iob18,005-tilegrid,all)) $(eval $(call fuzzer,030-iob18,005-tilegrid,all))
endif endif
$(eval $(call fuzzer,031-cmt-mmcm,005-tilegrid,all)) $(eval $(call fuzzer,031-cmt-mmcm,005-tilegrid,all))
$(eval $(call fuzzer,032-cmt-pll,005-tilegrid,all)) $(eval $(call fuzzer,032-cmt-pll,005-tilegrid,all))
$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid 071-ppips,all)) $(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid 071-ppips,all))
ifneq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
# FIXME: 034b fuzzer is generating conflicting bits around the FREQ_BB[N] bits. # FIXME: 034b fuzzer is generating conflicting bits around the FREQ_BB[N] bits.
# The fuzzer can be re-enabled once the conflicting bits are not generated anymore # The fuzzer can be re-enabled once the conflicting bits are not generated anymore
$(eval $(call fuzzer,034b-cmt-mmcm-pips,005-tilegrid 071-ppips,all)) $(eval $(call fuzzer,034b-cmt-mmcm-pips,005-tilegrid 071-ppips,all))
endif endif
$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid,all)) $(eval $(call fuzzer,035-iob-ilogic,005-tilegrid,all))
$(eval $(call fuzzer,035a-iob-idelay,005-tilegrid,all)) $(eval $(call fuzzer,035a-iob-idelay,005-tilegrid,all))
ifeq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,035a-iob18-idelay,005-tilegrid,all)) $(eval $(call fuzzer,035a-iob18-idelay,005-tilegrid,all))
endif endif
$(eval $(call fuzzer,035b-iob-iserdes,005-tilegrid,all)) $(eval $(call fuzzer,035b-iob-iserdes,005-tilegrid,all))
$(eval $(call fuzzer,036-iob-ologic,005-tilegrid,all)) $(eval $(call fuzzer,036-iob-ologic,005-tilegrid,all))
ifeq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,036-iob18-ologic,005-tilegrid,all)) $(eval $(call fuzzer,036-iob18-ologic,005-tilegrid,all))
endif endif
$(eval $(call fuzzer,037-iob-pips,005-tilegrid 035b-iob-iserdes,all)) $(eval $(call fuzzer,037-iob-pips,005-tilegrid 035b-iob-iserdes,all))
ifeq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,037-iob18-pips,005-tilegrid 035b-iob-iserdes,all)) $(eval $(call fuzzer,037-iob18-pips,005-tilegrid 035b-iob-iserdes,all))
endif endif
$(eval $(call fuzzer,038-cfg,005-tilegrid,all)) $(eval $(call fuzzer,038-cfg,005-tilegrid,all))
@ -148,7 +155,7 @@ $(eval $(call fuzzer,044-clk-bufg-pips,046-clk-bufg-muxed-pips,all))
$(eval $(call fuzzer,045-hclk-cmt-pips,005-tilegrid,all)) $(eval $(call fuzzer,045-hclk-cmt-pips,005-tilegrid,all))
$(eval $(call fuzzer,046-clk-bufg-muxed-pips,005-tilegrid,all)) $(eval $(call fuzzer,046-clk-bufg-muxed-pips,005-tilegrid,all))
$(eval $(call fuzzer,047-hclk-ioi-pips,005-tilegrid,all)) $(eval $(call fuzzer,047-hclk-ioi-pips,005-tilegrid,all))
ifeq ($(XRAY_DATABASE),kintex7) ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
$(eval $(call fuzzer,047-hclk-ioi18-pips,005-tilegrid,all)) $(eval $(call fuzzer,047-hclk-ioi18-pips,005-tilegrid,all))
endif endif
$(eval $(call fuzzer,047a-hclk-idelayctrl-pips,047-hclk-ioi-pips,all)) $(eval $(call fuzzer,047a-hclk-idelayctrl-pips,047-hclk-ioi-pips,all))

4
fuzzers/piplist/piplist.tcl
View File

@ -13,8 +13,8 @@ proc build_project {} {
read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
create_pblock roi create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

2
utils/update_parts.py
View File

@ -30,7 +30,7 @@ def main():
parser.add_argument( parser.add_argument(
'family', 'family',
help="Name of the device family.", help="Name of the device family.",
choices=['artix7', 'kintex7', 'zynq7', 'spartan7']) choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
util.db_root_arg(parser) util.db_root_arg(parser)
args = parser.parse_args() args = parser.parse_args()

2
utils/update_resources.py
View File

@ -30,7 +30,7 @@ def main():
parser.add_argument( parser.add_argument(
'family', 'family',
help="Name of the device family.", help="Name of the device family.",
choices=['artix7', 'kintex7', 'zynq7', 'spartan7']) choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
db_root_arg(parser) db_root_arg(parser)
args = parser.parse_args() args = parser.parse_args()

2
utils/update_resources.tcl
View File

@ -14,7 +14,7 @@ link_design -part $::env(XRAY_PART)
set clk_pins [get_package_pins -filter "IS_CLK_CAPABLE"] set clk_pins [get_package_pins -filter "IS_CLK_CAPABLE"]
# three pins -> 1, 2, 3 on HR banks only # three pins -> 1, 2, 3 on HR banks only
set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_RANGE"] set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_PERFORMANCE || BANK_TYPE==BT_HIGH_RANGE"]
set data_pins "" set data_pins ""
foreach bank [split $banks " "] { foreach bank [split $banks " "] {