mirror of https://github.com/openXC7/prjxray.git
116 lines
3.8 KiB
Tcl
116 lines
3.8 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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# write_checkpoint -force design.dcp
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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set fp [open "../../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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set tries_limit 10
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# each run can fail up to three times so we need to prepare 3*todo_lines tiles to work on
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set tiles [expr $tries_limit * [llength $todo_lines]]
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set int_l_tiles [randsample_list $tiles [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [randsample_list $tiles [filter [pblock_tiles roi] {TYPE == INT_R}]]
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set fp [open "design.txt" w]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set mynet [create_net mynet_$idx]
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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set tries 0
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while {1} {
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set tile_idx [expr $tries + [expr $idx * $tries_limit]]
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incr tries
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $tile_idx]; set other_tile [lindex $int_r_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $tile_idx]; set other_tile [lindex $int_l_tiles $idx]}
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puts "PIP Tile: $tile"
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set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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puts "LUT Tile (Site): $other_tile ($driver_site)"
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set_property -dict "LOC $driver_site BEL A6LUT" $mylut
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set rc [route_via $mynet "$tile/$src_wire $tile/$dst_wire" 0]
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if {$rc != 0} {
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puts "ROUTING DONE!"
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break
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}
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# fallback
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puts "WARNING: failed to route net"
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write_checkpoint -force route_todo_$idx.$tries.fail.dcp
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puts "Rolling back route"
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set_property is_route_fixed 0 $mynet
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set_property is_bel_fixed 0 $mylut
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set_property is_loc_fixed 1 $mylut
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route_design -unroute -nets $mynet
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# sometimes it gets stuck in specific src -> dst locations
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if {$tries >= $tries_limit} {
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error "WARNING: failed to route net after $tries tries"
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}
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}
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if {[get_pips -filter "NAME == \"${tile}/${tile_type}.${src_wire}<<->>${dst_wire}\" || NAME == \"${tile}/${tile_type}.${dst_wire}<<->>${src_wire}\"" -of_objects [get_nets $mynet]] != ""} {
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puts $fp "A $tile/$dst_wire $tile/$src_wire"
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}
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}
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route_design
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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puts $fp "B [get_wires -of_objects $pip]"
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}
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}
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close $fp
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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