diff --git a/Makefile b/Makefile
index d66c2c10..17e1fef0 100644
--- a/Makefile
+++ b/Makefile
@@ -136,7 +136,7 @@ check-license:
 # Targets related to Project X-Ray databases
 # ------------------------
 
-DATABASES=artix7 kintex7 zynq7 spartan7
+DATABASES=artix7 kintex7 zynq7 spartan7 virtex7
 
 define database
 
@@ -191,8 +191,9 @@ ARTIX_PARTS=artix7_50t artix7_200t
 ZYNQ_PARTS=zynq7010
 KINTEX_PARTS=kintex7_160t
 SPARTAN_PARTS=
+VIRTEX_PARTS=
 
-XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS}
+XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} ${VIRTEX_PARTS}
 
 define multiple-parts
 
@@ -245,6 +246,13 @@ db-extras-kintex7-roi: $(addprefix db-roi-only-,$(KINTEX_PARTS))
 db-extras-kintex7-harness:
 	@true
 
+db-extras-virtex7-parts: $(addprefix db-part-only-,$(VIRTEX_PARTS))
+
+db-extras-virtex7-roi: $(addprefix db-roi-only-,$(VIRTEX_PARTS))
+
+db-extras-virtex7-harness:
+	@true
+
 db-extras-spartan7-parts:
 	@true
 
diff --git a/fuzzers/001-part-yaml/generate.tcl b/fuzzers/001-part-yaml/generate.tcl
index a1409806..d50d77e2 100644
--- a/fuzzers/001-part-yaml/generate.tcl
+++ b/fuzzers/001-part-yaml/generate.tcl
@@ -29,10 +29,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog ../../top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile
index 57716950..f9323fad 100644
--- a/fuzzers/005-tilegrid/Makefile
+++ b/fuzzers/005-tilegrid/Makefile
@@ -6,13 +6,31 @@
 #
 # SPDX-License-Identifier: ISC
 
+
+ifeq (${XRAY_DATABASE}, virtex7)
+HAS_HIGH_PERFORMANCE_BANKS = 1
+# TODO: some virtex devices have high range banks
+HAS_HIGH_RANGE_BANKS = 0
+endif
+ifeq (${XRAY_DATABASE}, kintex7)
+# xc7k420t/xc7k480t have no high performance banks
+ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
+HAS_HIGH_PERFORMANCE_BANKS = 1
+else
+HAS_HIGH_PERFORMANCE_BANKS = 0
+endif
+endif
+
+
 FUZDIR=$(shell pwd)
 BUILD_FOLDER=build_${XRAY_PART}
 BUILD_DIR=$(FUZDIR)/$(BUILD_FOLDER)
 TILEGRID_TDB_DEPENDENCIES=
+ifeq (${HAS_HIGH_RANGE_BANKS}, 1)
 TILEGRID_TDB_DEPENDENCIES += iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+endif
 TILEGRID_TDB_DEPENDENCIES += monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@@ -48,9 +66,7 @@ TILEGRID_TDB_DEPENDENCIES += ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
 
 # Kintex7 only fuzzers
-ifeq (${XRAY_DATABASE}, kintex7)
-# xc7k420t/xc7k480t have no high performance banks
-ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
+ifeq (${HAS_HIGH_PERFORMANCE_BANKS}, 1)
 TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@@ -60,7 +76,6 @@ endif
 ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t))
 TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
-endif
 
 BASICDB_TILEGRID=$(BUILD_FOLDER)/basicdb/${XRAY_FABRIC}/tilegrid.json
 
diff --git a/fuzzers/005-tilegrid/bram/generate.tcl b/fuzzers/005-tilegrid/bram/generate.tcl
index 86d58a90..fb089658 100644
--- a/fuzzers/005-tilegrid/bram/generate.tcl
+++ b/fuzzers/005-tilegrid/bram/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/clb/generate.tcl b/fuzzers/005-tilegrid/clb/generate.tcl
index 17a6eb55..1fafcd13 100644
--- a/fuzzers/005-tilegrid/clb/generate.tcl
+++ b/fuzzers/005-tilegrid/clb/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/clb_int/generate.tcl b/fuzzers/005-tilegrid/clb_int/generate.tcl
index 268e600e..5b8bc6ea 100644
--- a/fuzzers/005-tilegrid/clb_int/generate.tcl
+++ b/fuzzers/005-tilegrid/clb_int/generate.tcl
@@ -12,8 +12,8 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/mmcm/generate.tcl b/fuzzers/005-tilegrid/mmcm/generate.tcl
index 198529a8..e859afea 100644
--- a/fuzzers/005-tilegrid/mmcm/generate.tcl
+++ b/fuzzers/005-tilegrid/mmcm/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/monitor/generate.tcl b/fuzzers/005-tilegrid/monitor/generate.tcl
index 86d58a90..fb089658 100644
--- a/fuzzers/005-tilegrid/monitor/generate.tcl
+++ b/fuzzers/005-tilegrid/monitor/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/ps7_int/generate.tcl b/fuzzers/005-tilegrid/ps7_int/generate.tcl
index 198529a8..e859afea 100644
--- a/fuzzers/005-tilegrid/ps7_int/generate.tcl
+++ b/fuzzers/005-tilegrid/ps7_int/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/005-tilegrid/util.tcl b/fuzzers/005-tilegrid/util.tcl
index 581b9945..90966747 100644
--- a/fuzzers/005-tilegrid/util.tcl
+++ b/fuzzers/005-tilegrid/util.tcl
@@ -85,7 +85,7 @@ proc make_io_pad_sites {} {
         if {[llength $site] == 0} {
             continue
         }
-        if [string match IOB33* [get_property SITE_TYPE $site]] {
+        if [string match IOB18* [get_property SITE_TYPE $site]] {
             dict append io_pad_sites $site $pad
         }
     }
@@ -114,10 +114,10 @@ proc make_iob_sites {} {
 }
 
 proc assign_iobs_old {} {
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 }
 
 proc assign_iobs {} {
@@ -129,9 +129,9 @@ proc assign_iobs {} {
     # Basic pins
     # XXX: not all pads are valid, but seems to be working for now
     # Maybe better to set to XRAY_PIN_* and take out of the list?
-    set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do]
-    set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS18" [get_ports do]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS18" [get_ports stb]
 
     # din bus
     set fixed_pins 3
@@ -139,7 +139,7 @@ proc assign_iobs {} {
     for {set i 0} {$i < [llength $iports]} {incr i} {
         set pad [lindex $iopad [expr $i+$fixed_pins]]
         set port [lindex $iports $i]
-        set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
+        set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS18" $port
     }
 }
 
diff --git a/fuzzers/007-timing/bel/runme.tcl b/fuzzers/007-timing/bel/runme.tcl
index 1c2c7abe..fa17fd54 100644
--- a/fuzzers/007-timing/bel/runme.tcl
+++ b/fuzzers/007-timing/bel/runme.tcl
@@ -13,8 +13,8 @@ proc create_design {} {
     read_verilog $::env(SRC_DIR)/top.v
     synth_design -top top -flatten_hierarchy none
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/007-timing/routing-bels/runme.tcl b/fuzzers/007-timing/routing-bels/runme.tcl
index 778108fc..8a5bdc36 100644
--- a/fuzzers/007-timing/routing-bels/runme.tcl
+++ b/fuzzers/007-timing/routing-bels/runme.tcl
@@ -13,8 +13,8 @@ proc create_design {} {
     read_verilog $::env(SRC_DIR)/top.v
     synth_design -top top -flatten_hierarchy none
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports do]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/010-clb-lutinit/generate.tcl b/fuzzers/010-clb-lutinit/generate.tcl
index 46731727..870b2d27 100644
--- a/fuzzers/010-clb-lutinit/generate.tcl
+++ b/fuzzers/010-clb-lutinit/generate.tcl
@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog ../../top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
 set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
         [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
diff --git a/fuzzers/011-clb-ffconfig/generate.tcl b/fuzzers/011-clb-ffconfig/generate.tcl
index c98df8a4..9e5d8fa1 100644
--- a/fuzzers/011-clb-ffconfig/generate.tcl
+++ b/fuzzers/011-clb-ffconfig/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/012-clb-n5ffmux/generate.tcl b/fuzzers/012-clb-n5ffmux/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/012-clb-n5ffmux/generate.tcl
+++ b/fuzzers/012-clb-n5ffmux/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/013-clb-ncy0/generate.tcl b/fuzzers/013-clb-ncy0/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/013-clb-ncy0/generate.tcl
+++ b/fuzzers/013-clb-ncy0/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/014-clb-ffsrcemux/generate.tcl b/fuzzers/014-clb-ffsrcemux/generate.tcl
index 20c0456e..461a622c 100644
--- a/fuzzers/014-clb-ffsrcemux/generate.tcl
+++ b/fuzzers/014-clb-ffsrcemux/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/015-clb-nffmux/generate.tcl b/fuzzers/015-clb-nffmux/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/015-clb-nffmux/generate.tcl
+++ b/fuzzers/015-clb-nffmux/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/016-clb-noutmux/generate.tcl b/fuzzers/016-clb-noutmux/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/016-clb-noutmux/generate.tcl
+++ b/fuzzers/016-clb-noutmux/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/017-clb-precyinit/generate.tcl b/fuzzers/017-clb-precyinit/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/017-clb-precyinit/generate.tcl
+++ b/fuzzers/017-clb-precyinit/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/018-clb-ram/generate.tcl b/fuzzers/018-clb-ram/generate.tcl
index fc0308ea..45ecd188 100644
--- a/fuzzers/018-clb-ram/generate.tcl
+++ b/fuzzers/018-clb-ram/generate.tcl
@@ -10,10 +10,10 @@ proc build {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
     create_pblock roi
 
diff --git a/fuzzers/019-clb-ndi1mux/generate.tcl b/fuzzers/019-clb-ndi1mux/generate.tcl
index 79425b3f..9efe5693 100644
--- a/fuzzers/019-clb-ndi1mux/generate.tcl
+++ b/fuzzers/019-clb-ndi1mux/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/025-bram-config/generate.tcl b/fuzzers/025-bram-config/generate.tcl
index ef8cd739..26e4cdf1 100644
--- a/fuzzers/025-bram-config/generate.tcl
+++ b/fuzzers/025-bram-config/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/025-bram-config/minitest/runme.tcl b/fuzzers/025-bram-config/minitest/runme.tcl
index 957aaf0e..1fe66461 100644
--- a/fuzzers/025-bram-config/minitest/runme.tcl
+++ b/fuzzers/025-bram-config/minitest/runme.tcl
@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/026-bram-data/minitest/runme.tcl b/fuzzers/026-bram-data/minitest/runme.tcl
index 957aaf0e..1fe66461 100644
--- a/fuzzers/026-bram-data/minitest/runme.tcl
+++ b/fuzzers/026-bram-data/minitest/runme.tcl
@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/030-iob/minitest/runme.tcl b/fuzzers/030-iob/minitest/runme.tcl
index 6ce1d198..505a9869 100644
--- a/fuzzers/030-iob/minitest/runme.tcl
+++ b/fuzzers/030-iob/minitest/runme.tcl
@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 # set_property roi/dut
 
diff --git a/fuzzers/030-iob/minitest/template.tcl b/fuzzers/030-iob/minitest/template.tcl
index 24ffeaeb..ca6a549c 100644
--- a/fuzzers/030-iob/minitest/template.tcl
+++ b/fuzzers/030-iob/minitest/template.tcl
@@ -11,10 +11,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(TOP_V)
 synth_design -top top -flatten_hierarchy none
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
@@ -27,6 +27,6 @@ route_design
 write_checkpoint -force design.dcp
 
 # set port [create_port -direction OUT myport]
-# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
+# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS18" $port
 # set_property PULLTYPE PULLUP $port
 # set_property PULLTYPE PULLDOWN $port
diff --git a/fuzzers/033-mon-xadc/generate.tcl b/fuzzers/033-mon-xadc/generate.tcl
index c0508a0a..0cb532b5 100644
--- a/fuzzers/033-mon-xadc/generate.tcl
+++ b/fuzzers/033-mon-xadc/generate.tcl
@@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/038-cfg/generate.tcl b/fuzzers/038-cfg/generate.tcl
index f4caaa39..e49f6f78 100644
--- a/fuzzers/038-cfg/generate.tcl
+++ b/fuzzers/038-cfg/generate.tcl
@@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports do]
 
 create_pblock roi
 
diff --git a/fuzzers/050-pip-seed/generate.tcl b/fuzzers/050-pip-seed/generate.tcl
index 8830ae0d..773e5fad 100644
--- a/fuzzers/050-pip-seed/generate.tcl
+++ b/fuzzers/050-pip-seed/generate.tcl
@@ -15,10 +15,10 @@ read_verilog $::env(FUZDIR)/picorv32.v
 puts "FUZ([pwd]): Synth design"
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports din]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports dout]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
 create_pblock roi
 add_cells_to_pblock [get_pblocks roi] [get_cells roi]
diff --git a/fuzzers/051-pip-imuxlout-bypalts/generate.tcl b/fuzzers/051-pip-imuxlout-bypalts/generate.tcl
index 0ef7478f..f703946b 100644
--- a/fuzzers/051-pip-imuxlout-bypalts/generate.tcl
+++ b/fuzzers/051-pip-imuxlout-bypalts/generate.tcl
@@ -13,10 +13,10 @@ read_verilog $::env(FUZDIR)/top.v
 read_verilog $::env(FUZDIR)/picorv32.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports din]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports dout]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/052-pip-clkin/generate.tcl b/fuzzers/052-pip-clkin/generate.tcl
index 012d6454..eb6dc76b 100644
--- a/fuzzers/052-pip-clkin/generate.tcl
+++ b/fuzzers/052-pip-clkin/generate.tcl
@@ -43,8 +43,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/053-pip-ctrlin/generate.tcl b/fuzzers/053-pip-ctrlin/generate.tcl
index 8986bfef..5cbe6159 100644
--- a/fuzzers/053-pip-ctrlin/generate.tcl
+++ b/fuzzers/053-pip-ctrlin/generate.tcl
@@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/054-pip-fan-alt/generate.tcl b/fuzzers/054-pip-fan-alt/generate.tcl
index 7b913bf9..d06b4238 100644
--- a/fuzzers/054-pip-fan-alt/generate.tcl
+++ b/fuzzers/054-pip-fan-alt/generate.tcl
@@ -13,8 +13,8 @@ proc build_basic {} {
     read_verilog $::env(FUZDIR)/top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
     create_pblock roi
     resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/055-pip-gnd/generate.tcl b/fuzzers/055-pip-gnd/generate.tcl
index 98274692..8852ded4 100644
--- a/fuzzers/055-pip-gnd/generate.tcl
+++ b/fuzzers/055-pip-gnd/generate.tcl
@@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/056-pip-rem/generate.tcl b/fuzzers/056-pip-rem/generate.tcl
index 500701b6..31c41d5a 100644
--- a/fuzzers/056-pip-rem/generate.tcl
+++ b/fuzzers/056-pip-rem/generate.tcl
@@ -25,8 +25,8 @@ proc build_basic {} {
     read_verilog $::env(FUZDIR)/top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
     create_pblock roi
     resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/057-pip-bi/bipiplist.tcl b/fuzzers/057-pip-bi/bipiplist.tcl
index 3e2b6f87..3279a585 100644
--- a/fuzzers/057-pip-bi/bipiplist.tcl
+++ b/fuzzers/057-pip-bi/bipiplist.tcl
@@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) bipiplist bipiplist
 read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/057-pip-bi/generate.tcl b/fuzzers/057-pip-bi/generate.tcl
index 7ea37b87..097fba48 100644
--- a/fuzzers/057-pip-bi/generate.tcl
+++ b/fuzzers/057-pip-bi/generate.tcl
@@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/058-pip-hclk/generate.tcl b/fuzzers/058-pip-hclk/generate.tcl
index 2fa207b2..935b65f6 100644
--- a/fuzzers/058-pip-hclk/generate.tcl
+++ b/fuzzers/058-pip-hclk/generate.tcl
@@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/059-pip-byp-bounce/generate.tcl b/fuzzers/059-pip-byp-bounce/generate.tcl
index 7b913bf9..d06b4238 100644
--- a/fuzzers/059-pip-byp-bounce/generate.tcl
+++ b/fuzzers/059-pip-byp-bounce/generate.tcl
@@ -13,8 +13,8 @@ proc build_basic {} {
     read_verilog $::env(FUZDIR)/top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
     create_pblock roi
     resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl
index a4243801..5ed69d60 100644
--- a/fuzzers/071-ppips/generate.tcl
+++ b/fuzzers/071-ppips/generate.tcl
@@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog $::env(FUZDIR)/top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports a]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports y]
 
 create_pblock roi
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/fuzzers/100-dsp-mskpat/generate.tcl b/fuzzers/100-dsp-mskpat/generate.tcl
index 12504afd..32ed6f80 100644
--- a/fuzzers/100-dsp-mskpat/generate.tcl
+++ b/fuzzers/100-dsp-mskpat/generate.tcl
@@ -12,10 +12,10 @@ proc run {} {
     read_verilog top.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/fuzzers/Makefile b/fuzzers/Makefile
index 94a10949..18169816 100644
--- a/fuzzers/Makefile
+++ b/fuzzers/Makefile
@@ -95,6 +95,13 @@ all:: 005-tilegrid/run.ok
 endif
 
 ifneq ($(XRAY_DATABASE),kintex7)
+    HAS_HIGH_PERFORMANCE_BANKS = 1
+endif
+ifneq ($(XRAY_DATABASE),virtex7)
+    HAS_HIGH_PERFORMANCE_BANKS = 1
+endif
+
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,007-timing,005-tilegrid,all))
 endif
 $(eval $(call fuzzer,010-clb-lutinit,005-tilegrid,all))
@@ -113,29 +120,29 @@ $(eval $(call fuzzer,027-bram36-config,005-tilegrid,all))
 $(eval $(call fuzzer,028-fifo-config,005-tilegrid,all))
 $(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid,all))
 $(eval $(call fuzzer,030-iob,005-tilegrid,all))
-ifeq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,030-iob18,005-tilegrid,all))
 endif
 $(eval $(call fuzzer,031-cmt-mmcm,005-tilegrid,all))
 $(eval $(call fuzzer,032-cmt-pll,005-tilegrid,all))
 $(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid 071-ppips,all))
-ifneq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 # FIXME: 034b fuzzer is generating conflicting bits around the FREQ_BB[N] bits.
 # The fuzzer can be re-enabled once the conflicting bits are not generated anymore
 $(eval $(call fuzzer,034b-cmt-mmcm-pips,005-tilegrid 071-ppips,all))
 endif
 $(eval $(call fuzzer,035-iob-ilogic,005-tilegrid,all))
 $(eval $(call fuzzer,035a-iob-idelay,005-tilegrid,all))
-ifeq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,035a-iob18-idelay,005-tilegrid,all))
 endif
 $(eval $(call fuzzer,035b-iob-iserdes,005-tilegrid,all))
 $(eval $(call fuzzer,036-iob-ologic,005-tilegrid,all))
-ifeq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,036-iob18-ologic,005-tilegrid,all))
 endif
 $(eval $(call fuzzer,037-iob-pips,005-tilegrid 035b-iob-iserdes,all))
-ifeq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,037-iob18-pips,005-tilegrid 035b-iob-iserdes,all))
 endif
 $(eval $(call fuzzer,038-cfg,005-tilegrid,all))
@@ -148,7 +155,7 @@ $(eval $(call fuzzer,044-clk-bufg-pips,046-clk-bufg-muxed-pips,all))
 $(eval $(call fuzzer,045-hclk-cmt-pips,005-tilegrid,all))
 $(eval $(call fuzzer,046-clk-bufg-muxed-pips,005-tilegrid,all))
 $(eval $(call fuzzer,047-hclk-ioi-pips,005-tilegrid,all))
-ifeq ($(XRAY_DATABASE),kintex7)
+ifdef $(HAS_HIGH_PERFORMANCE_BANKS)
 $(eval $(call fuzzer,047-hclk-ioi18-pips,005-tilegrid,all))
 endif
 $(eval $(call fuzzer,047a-hclk-idelayctrl-pips,047-hclk-ioi-pips,all))
diff --git a/fuzzers/piplist/piplist.tcl b/fuzzers/piplist/piplist.tcl
index e2ed5075..3df8fdd7 100644
--- a/fuzzers/piplist/piplist.tcl
+++ b/fuzzers/piplist/piplist.tcl
@@ -13,8 +13,8 @@ proc build_project {} {
     read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
     synth_design -top top
 
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports i]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports o]
 
     create_pblock roi
     resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
diff --git a/utils/update_parts.py b/utils/update_parts.py
index 407eee13..0b0c519a 100755
--- a/utils/update_parts.py
+++ b/utils/update_parts.py
@@ -30,7 +30,7 @@ def main():
     parser.add_argument(
         'family',
         help="Name of the device family.",
-        choices=['artix7', 'kintex7', 'zynq7', 'spartan7'])
+        choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
     util.db_root_arg(parser)
 
     args = parser.parse_args()
diff --git a/utils/update_resources.py b/utils/update_resources.py
index bc5c8f54..c813eaa7 100755
--- a/utils/update_resources.py
+++ b/utils/update_resources.py
@@ -30,7 +30,7 @@ def main():
     parser.add_argument(
         'family',
         help="Name of the device family.",
-        choices=['artix7', 'kintex7', 'zynq7', 'spartan7'])
+        choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
     db_root_arg(parser)
 
     args = parser.parse_args()
diff --git a/utils/update_resources.tcl b/utils/update_resources.tcl
index 292041db..e7300e3f 100644
--- a/utils/update_resources.tcl
+++ b/utils/update_resources.tcl
@@ -14,7 +14,7 @@ link_design -part $::env(XRAY_PART)
 set clk_pins [get_package_pins -filter "IS_CLK_CAPABLE"]
 
 # three pins -> 1, 2, 3 on HR banks only
-set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_RANGE"]
+set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_PERFORMANCE || BANK_TYPE==BT_HIGH_RANGE"]
 
 set data_pins ""
 foreach bank [split $banks " "] {