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prjxray/minitests/litex/uart_ddr/arty/src.yosys/synth.ys

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uart-ddr: addressed review comments and fixed file locations Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-02-04 11:10:40 +01:00
read_verilog ../generated/top.v
Added UART DDR minitest Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-02-03 12:30:42 +01:00
synth_xilinx -edif top.edif