e8eab9a45b
Bump chip database
2026-03-18 13:13:58 +01:00
6572d46414
Allowing the assignment of TDO pin (IO_S3_B3) on the second die for A2 ( #18 )
...
* JTAG Pins also exist on 1B Die. Allow the S3 Bank to be assigned to the second Die
* Add attribute pins to class Bank, defining the list of allowed pins
* Potential fix for pull request finding
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
* Generate white list for WA Bank
---------
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
2026-03-18 13:13:11 +01:00
bc3df10ff3
Add alternate clock routes and CP pass through [sc-184] ( #17 )
...
* Add alternate clock routes
* Add pins for alternate signals
* Add more pips and placeholder for metadata
* Add data/mask for pips
* Add pips for testing
* fix CPE_CPLINES OUTx inputs
* resources
* Added rest of CP lines pips
* Change to block and resource
* Fix chip database error
* Timing data for CP lines
* Fix bitstream
* Bump database version
2026-02-25 08:11:36 +01:00
8f0b8a06f2
Extending for LUT permutation ( #14 )
2025-12-22 15:10:11 +01:00
1901f4b833
Bump chip database version
2025-11-10 12:00:22 +01:00
f081ba87cb
Bump version to 1.9
2025-10-17 11:56:29 +02:00
867835f7bb
Better naming for D2D and pass trough TES as on hardware
2025-10-07 13:11:27 +02:00
36f6b5eec4
Bump version to 1.8
2025-09-23 08:08:07 +02:00
5bae9cae91
del_dummy is default delay
2025-09-11 15:21:09 +02:00
5a03c49c49
sortout multidie connections
2025-09-11 15:07:57 +02:00
eae068fa3e
fix
2025-09-11 11:49:06 +02:00
56c2bed294
Cleanup BRAM
2025-09-04 15:57:16 +02:00
f6654f83a7
bump chipdb
2025-09-02 14:04:37 +02:00
d04286b39a
bump database version
2025-08-29 14:57:41 +02:00
6ad315609d
Bump database version
2025-08-14 11:53:29 +02:00
10b52f37f1
Added IOSEL
2025-08-13 15:49:44 +02:00
0fb182de18
rename to match port names
2025-08-13 12:52:04 +02:00
2983a7f4ff
Bump database version
2025-07-07 10:12:59 +02:00
ff2445f353
Add D2D support
2025-06-18 08:31:49 +02:00
08b35c4538
Add DDR pin information
2025-06-18 08:31:49 +02:00
a0afc3aea3
Fixed wrong bank mapping
2025-06-18 08:31:49 +02:00
58a098407b
Bump version to 1.2
2025-06-18 08:31:49 +02:00
bce9877556
Create CLKIN and GLBOUT as primitives
2025-06-18 08:31:49 +02:00
5b9b1d013e
Add timing modification delays
2025-06-02 11:18:16 +02:00
7800a49b4d
Export database version
2025-05-27 15:23:16 +02:00
91eca20d10
Add timing information from dly files
2025-05-27 15:21:14 +02:00
2645240bf9
Add flags for clock source
2025-03-18 09:20:12 +01:00
74197786e5
Export pad bank information
2025-03-13 12:12:40 +01:00
017722609d
Add DDR connections
2025-02-06 08:56:32 +01:00
c62215338f
Expose extra tile information
2025-01-23 12:52:36 +01:00
d2aaea4adb
Made data classes able to be ordered
2025-01-14 15:15:40 +01:00
da2dfca641
Extract pads on multi die
2024-12-27 14:33:52 +01:00
3ed3e9a83b
Wrap connections in Die class
2024-12-27 10:42:38 +01:00
65f22ed13e
Create connections in all dies
2024-12-27 10:03:19 +01:00
e22d59f669
Start adding multi die support
2024-12-27 09:01:22 +01:00
Miodrag Milanovic
Hai Luong