c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
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Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
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Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
c417ce6746
lattice: spi_put: avoid loop when tx == NULL
2023-09-06 15:50:28 +02:00
61b59ce827
jtag: fix state machine (issue introduce by commit 9e91c3)
2023-09-06 15:47:32 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
0f3afbcaea
Make IDCODE unsigned
2023-08-29 20:01:21 +03:00
8976404b78
Use JTAG state
2023-08-29 20:00:28 +03:00
1908ccd83b
make output buffer const
2023-08-29 19:51:41 +03:00
0de2ea6b39
gowin: add preliminary support for GW5AST-138
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Arora V series is a new series of Gowin FPGA, in which the flashing
process has changed.
Add preliminary support by adding FS file line count and deal with the
SRAM writing process. Flash writing is not yet done.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-12 12:36:06 +08:00
6a4e107e42
part: add known ID codes for GW5 series
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Codes are from Gowin UG704.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-09 22:11:41 +08:00
9d22d62a54
part/board: adding Avnet Mini-ITX
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Adding the Avnet Mini-ITX dev board that uses the XC7Z100 Zynq-7000
device.
2023-08-07 17:06:02 +01:00
e3c8d6be1d
board: added QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
2023-08-05 11:49:53 +02:00
7424ea2af9
part: update altera/intel idcode (same idcode for III/IV/10 LP)
2023-08-05 06:47:51 +02:00
baff0cad1e
src/part: Fix Xilinx XC2 ident.
2023-08-03 16:12:51 +02:00
502f38fb00
src/part.hpp: Add Kintex Ultrascale+ KU3P ID-Code.
2023-08-03 16:07:55 +02:00
4042646434
src/part.hpp: Add separator for each vendor.
2023-08-03 16:07:43 +02:00
c3e0707f6b
src/part.hpp: Reorder families (older first, smaller first) and minor alignment cleanups.
2023-08-03 16:07:33 +02:00
a1dea79230
src/part.hpp: Add separator for each chip family.
2023-08-03 16:07:24 +02:00
4c5f6f361b
svf_jtag: fix -Wmismatched-new-delete delete -> delete[]
2023-08-03 07:53:59 +02:00
6ef87c5466
ftdipp_mpsse: fix format-zero-length snprintf -> memset
2023-08-03 07:43:56 +02:00
0e1e07262c
ftdispi: add missing status_pin
2023-08-03 07:42:06 +02:00
2f8056cba5
usbBlaster: cleanup
2023-07-30 08:54:13 +02:00
75d98d12e9
jtag: merge init_internal to CTOR, pass verbose to jtag drivers
2023-07-30 08:45:57 +02:00
4bf4b94bbb
cables: verbose type coherency
2023-07-30 08:39:15 +02:00
469e1c3669
efinix: remove verbose comparison
2023-07-30 07:28:29 +02:00
76f84c1190
ftdipp_mpsse: _verbose int8_t -> bool
2023-07-30 07:23:19 +02:00
c41ef7539c
ftdispi: convert verbose bool -> int8_t
2023-07-30 07:19:17 +02:00
baeb9d52ec
Merge pull request #358 from inkdot7/decimal_busdev
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Parse USB bus:dev as decimal integers, to be consistent with `--scan-usb`.
2023-07-29 18:10:48 +02:00
bed17f3be8
Parse USB bus:dev as decimal integers, to be consistent with --scan-usb.
...
Do not accept auto-detected base 0 (e.g. prefix '0x' for hex), since '0'
prefix gives an octal interpretation, and the user is likely to copy
values from `--scan-usb` or `lsusb` that could then be misinterpreted,
e.g. 005:010.
2023-07-29 09:49:52 +02:00
4f7a4c33aa
Tell USB bus and address when ftdi open fails, when bus and addr both non-zero.
2023-07-29 08:52:16 +02:00
3955a70843
jtag: fix warning (uninitialized tms)
2023-07-27 07:39:20 +02:00
ab9eff7412
jlink: fix warning (uninitialized length)
2023-07-27 07:35:14 +02:00
1dba0572ff
lattice: fix warning (uninitialized rx_buf)
2023-07-27 07:18:59 +02:00
a1e9d3f7db
main: (SPI mode) sanity check: print error and quit when manufacturer is unknown
2023-07-27 07:15:49 +02:00
a89fc54f29
cable: ch347: fix for CI (libusb_strerror with a cast in -> libusb_error, fix libusb callback signature)
2023-07-26 08:37:39 +02:00
0fc8ba10a8
Add WCH CH347T(mode #3 ) JTAG cable
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2023-07-26 08:17:57 +02:00
Zhongyi Chen
Alexey Starikovskiy
Gwenhael Goavec-Merou
Rodrigo Rengifo
Icenowy Zheng
Shareef Jalloq
Florent Kermarrec
Haakan T Johansson