803bdfecce
altera: MAX10: added --flash-sector support with arbitrary binary file
2025-06-18 18:57:26 +02:00
10fbb8a153
doc/FPGAs,doc/vendors/lattice: added Lattice ECP3
2025-06-18 16:25:40 +02:00
719b420a11
doc/vendors/intel.rst: fixed section/subsection for MAX10
2025-04-03 21:55:28 +02:00
5bbc93e725
doc/vendors/intel.rst: improved MAX10 section
2025-04-03 21:51:25 +02:00
7dac3ef447
altera: first draft for max10 native support (with pof and only for internal flash)
2024-12-31 18:42:52 +01:00
ffa006d0ee
Add 'user-flash' CLI argument
2024-12-11 12:01:37 +01:00
c0faf48d46
Update Max II and Cyclone II documentation ( #493 )
...
Co-authored-by: sab <sab@debian.shadow>
2024-10-19 06:27:49 +02:00
ad01d986c1
adding support for cyc5000
2024-08-24 21:32:00 -07:00
28dbf42d5b
doc/vendors/xilinx: adding a note for Zynq devices
2023-07-31 16:48:20 +02:00
87b17ed9bf
efinix: support using JTAG interfaces
2023-06-01 11:05:26 +10:00
9331bf7a6b
add sipeed tang nano 20k
2023-05-25 19:24:48 +08:00
4161c79920
Add Support for Xilinx KCU116 ( #322 )
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* initial kcu116 support
* add kintex ultrascale plus family to xilinx.cpp
* add docs
* combine xcku and xcvu check
* rebuild bitstream for -1 speedgrade
2023-03-09 20:48:19 +01:00
7697341a68
Add documentation for Xilinx SPIx8 mode
2023-02-14 11:44:45 +01:00
0591af56b7
feat(board): add support for Trenz C10LP-RefKit
2022-12-25 15:53:45 -06:00
0bdef7bab1
typo's, added git as dependency
2022-12-18 13:56:54 +01:00
6dfc762b7c
src/lattice: allows to use bit file for machxo2
2022-11-26 12:11:41 +01:00
6c28318057
doc: typo
2022-07-26 08:33:53 +02:00
a7279e1dd5
doc: Gowin: adding a note on howto recover the jtag when JTAGSSEL_N is used as GPIO
2022-07-26 08:18:44 +02:00
958ce4d4c3
--flash-sector CFG0 for MachXO3D and more information for its Breakout Board
2022-06-10 13:32:15 +02:00
bbef5b2e1e
doc/intel: fix svf generation command (issue #212 )
2022-04-11 19:14:18 +02:00
dce9406599
gatemate: fix failed signal polarity and update documentation
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* CFG_FAILED signal is no longer inverted
* minor fix in CFG_MD settings in doc/vendors/colognechip.rst
* update evaluation board URL
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2022-04-09 13:08:57 +02:00
49e6602b9f
colognechip integration: update vendor documentation
2021-12-10 12:41:33 +01:00
d09e5da0ba
colognechip integration: initial commit
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This commit adds support for the Cologne Chip GateMate FPGA series. Both
Evaluation Board and Programmer Cable are supported. Configurations can be
loaded into the FPGA with both devices via JTAG or SPI. In addition to
reading/writing data from/to flashes directly via SPI, this can also be done
via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware
and flash is no longer necessary in this case.
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-12-10 12:12:32 +01:00
2cb92af70f
doc: convert vendor notes from md to rst
2021-11-28 10:20:43 +01:00
Gwenhael Goavec-Merou
Jean THOMAS
ROOT
Greg Steiert
Andrew Dennison
wonderfullook
Maik Ender
Ricardo Barbedo
Marcus Andrade
Cedric de Wijs
Dennis Gnad
Patrick Urban
umarcor