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gatemate: fix failed signal polarity and update documentation 

* CFG_FAILED signal is no longer inverted
* minor fix in CFG_MD settings in doc/vendors/colognechip.rst
* update evaluation board URL

Signed-off-by: Patrick Urban <patrick.urban@web.de>
This commit is contained in:
Patrick Urban 2022-04-09 13:08:57 +02:00
parent 08c460135e
commit dce9406599
4 changed files with 17 additions and 17 deletions
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4
doc/boards.yml
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@ -96,14 +96,14 @@
- ID: gatemate_evb_jtag
Description: Cologne Chip GateMate FPGA Evaluation Board (JTAG mode)
URL: https://colognechip.com/programmable-logic/gatemate/
URL: https://colognechip.com/programmable-logic/gatemate-evaluation-board/
FPGA: Cologne Chip GateMate Series
Memory: OK
Flash: OK
- ID: gatemate_evb_spi
Description: Cologne Chip GateMate FPGA Evaluation Board (SPI mode)
URL: https://colognechip.com/programmable-logic/gatemate/
URL: https://colognechip.com/programmable-logic/gatemate-evaluation-board/
FPGA: Cologne Chip GateMate Series
Memory: OK
Flash: OK

10
doc/vendors/colognechip.rst vendored
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@ -17,7 +17,7 @@ Supported configuration files are bitfiles ``*.bit`` and it's ASCII equivalents
JTAG Configuration
------------------
Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xF0 (JTAG).
Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG).
1. Program using Evaluation Board:
@ -34,7 +34,7 @@ Performs an active hardware reset and writes the configuration into the FPGA lat
SPI Configuration
-----------------
Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0x40 (SPI passive).
Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0x4 (SPI passive).
1. Program using Evaluation Board:
@ -51,7 +51,7 @@ Performs an active hardware reset and writes the configuration into the FPGA lat
JTAG Flash Access
-----------------
It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xF0 (JTAG). Note that the FPGA will not start automatically.
It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG). Note that the FPGA will not start automatically.
1. Write to flash using Evaluation Board:
@ -74,7 +74,7 @@ The `offset` parameter can be used to store data at any point in the flash, e.g.
SPI Flash Access
----------------
If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins ``CFG_MD[3:0]`` set to 0x00 (SPI active).
If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins ``CFG_MD[3:0]`` set to 0x0 (SPI active).
1. Write to flash using Evaluation Board:
@ -92,4 +92,4 @@ The `offset` parameter can be used to store data at any point in the flash, e.g.
.. code-block:: bash
openFPGALoader -b gatemate_evb_spi -o <offset> <bitfile>.cfg.bit
openFPGALoader -b gatemate_evb_spi -o <offset> <bitfile>.cfg.bit

16
src/colognechip.cpp
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@ -12,13 +12,13 @@
CologneChip::CologneChip(FtdiSpi *spi, const std::string &filename,
const std::string &file_type, Device::prog_type_t prg_type,
uint16_t rstn_pin, uint16_t done_pin, uint16_t failn_pin, uint16_t oen_pin,
uint16_t rstn_pin, uint16_t done_pin, uint16_t fail_pin, uint16_t oen_pin,
bool verify, int8_t verbose) :
Device(NULL, filename, file_type, verify, verbose), _rstn_pin(rstn_pin),
_done_pin(done_pin), _failn_pin(failn_pin), _oen_pin(oen_pin)
_done_pin(done_pin), _fail_pin(fail_pin), _oen_pin(oen_pin)
{
_spi = spi;
_spi->gpio_set_input(_done_pin | _failn_pin);
_spi->gpio_set_input(_done_pin | _fail_pin);
_spi->gpio_set_output(_rstn_pin | _oen_pin);
_ftdi_jtag = nullptr;
@ -49,13 +49,13 @@ CologneChip::CologneChip(Jtag* jtag, const std::string &filename,
/* pin configurations valid for both evaluation board and programer */
_rstn_pin = spi_board->reset_pin;
_done_pin = spi_board->done_pin;
_failn_pin = DBUS6;
_fail_pin = DBUS6;
_oen_pin = spi_board->oe_pin;
/* cast _jtag->_jtag from JtagInterface to FtdiJtagMPSSE to access GPIO */
_ftdi_jtag = reinterpret_cast<FtdiJtagMPSSE *>(_jtag->_jtag);
_ftdi_jtag->gpio_set_input(_done_pin | _failn_pin);
_ftdi_jtag->gpio_set_input(_done_pin | _fail_pin);
_ftdi_jtag->gpio_set_output(_rstn_pin | _oen_pin);
if (prg_type == Device::WR_SRAM) {
@ -82,8 +82,8 @@ void CologneChip::reset()
}
/**
* Obtain CFG_DONE and ~CFG_FAILED signals. Configuration is successfull iff
* CFG_DONE=true and ~CFG_FAILED=false.
* Obtain CFG_DONE and CFG_FAILED signals. Configuration is successfull iff
* CFG_DONE=true and CFG_FAILED=false.
*/
bool CologneChip::cfgDone()
{
@ -94,7 +94,7 @@ bool CologneChip::cfgDone()
status = _ftdi_jtag->gpio_get(true);
}
bool done = (status & _done_pin) > 0;
bool fail = (status & _failn_pin) == 0;
bool fail = (status & _fail_pin) > 0;
return (done && !fail);
}

4
src/colognechip.hpp
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@ -24,7 +24,7 @@ class CologneChip: public Device, SPIInterface {
public:
CologneChip(FtdiSpi *spi, const std::string &filename,
const std::string &file_type, Device::prog_type_t prg_type,
uint16_t rstn_pin, uint16_t done_pin, uint16_t failn_pin, uint16_t oen_pin,
uint16_t rstn_pin, uint16_t done_pin, uint16_t fail_pin, uint16_t oen_pin,
bool verify, int8_t verbose);
CologneChip(Jtag* jtag, const std::string &filename,
const std::string &file_type, Device::prog_type_t prg_type,
@ -64,7 +64,7 @@ class CologneChip: public Device, SPIInterface {
FtdiJtagMPSSE *_ftdi_jtag = NULL;
uint16_t _rstn_pin;
uint16_t _done_pin;
uint16_t _failn_pin;
uint16_t _fail_pin;
uint16_t _oen_pin;
};