altera: first draft for max10 native support (with pof and only for internal flash)
This commit is contained in:
Gwenhael Goavec-Merou
parent
01039bc710
commit
7dac3ef447
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@ -139,7 +139,7 @@ Intel:
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Model: 10M08
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URL: https://www.intel.fr/content/www/fr/fr/products/details/fpga/max/10.html
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Memory: SVF
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Flash: SVF
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Flash: POF
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Lattice:
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@ -55,7 +55,7 @@ with ``boardname`` = ``de0``, ``cyc1000``, ``c10lp-refkit``, ``de0nano``, ``de0n
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SPI flash
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---------
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RPD and RBF are supported.
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RPD and RBF are supported. POF is only supported for MAX10 (internal flash).
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``pof`` to ``rpd``:
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@ -82,8 +82,10 @@ file load:
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with ``boardname`` = ``cyc1000``, ``c10lp-refkit``.
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MAX10:
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.. code-block:: bash
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openFPGALoader -b boardname project_name_auto.pof
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Intel/Altera (Old Boards)
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=========================
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400
src/altera.cpp
400
src/altera.cpp
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@ -15,6 +15,7 @@
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#include "epcq.hpp"
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#include "progressBar.hpp"
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#include "rawParser.hpp"
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#include "pofParser.hpp"
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#if defined (_WIN64) || defined (_WIN32)
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#include "pathHelper.hpp"
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#endif
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@ -34,7 +35,7 @@ Altera::Altera(Jtag *jtag, const std::string &filename,
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SPIInterface(filename, verbose, 256, verify, skip_load_bridge,
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skip_reset),
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_device_package(device_package), _spiOverJtagPath(spiOverJtagPath),
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_vir_addr(0x1000), _vir_length(14)
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_vir_addr(0x1000), _vir_length(14), _clk_period(1)
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{
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if (prg_type == Device::RD_FLASH) {
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_mode = Device::READ_MODE;
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@ -48,6 +49,8 @@ Altera::Altera(Jtag *jtag, const std::string &filename,
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_mode = Device::MEM_MODE;
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else
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_mode = Device::SPI_MODE;
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} else if (_file_extension == "pof") { // MAX10
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_mode = Device::FLASH_MODE;
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} else { // unknown type -> sanity check
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if (prg_type == Device::WR_SRAM) {
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printError("file has an unknown type:");
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@ -61,6 +64,16 @@ Altera::Altera(Jtag *jtag, const std::string &filename,
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}
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}
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}
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/* check device family */
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_idcode = _jtag->get_target_device_id();
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string family = fpga_list[_idcode].family;
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if (family == "MAX 10") {
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_fpga_family = MAX10_FAMILY;
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} else {
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_fpga_family = CYCLONE_MISC; // FIXME
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}
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}
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Altera::~Altera()
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@ -80,8 +93,6 @@ void Altera::programMem(RawParser &_bit)
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int byte_length = _bit.getLength()/8;
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const uint8_t *data = _bit.getData();
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uint32_t clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
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unsigned char cmd[2];
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unsigned char tx[864/8], rx[864/8];
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@ -95,7 +106,7 @@ void Altera::programMem(RawParser &_bit)
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_jtag->shiftIR(cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
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/* RUNTEST IDLE 12000 TCK ENDSTATE IDLE; */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000000/clk_period);
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_jtag->toggleClk(1000000/_clk_period);
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/* write */
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ProgressBar progress("Load SRAM", byte_length, 50, _quiet);
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@ -122,7 +133,7 @@ void Altera::programMem(RawParser &_bit)
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_jtag->shiftIR(cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
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/* RUNTEST 60 TCK; */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5000/clk_period);
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_jtag->toggleClk(5000/_clk_period);
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/*
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* SDR 864 TDI
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* (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)
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@ -138,7 +149,7 @@ void Altera::programMem(RawParser &_bit)
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_jtag->shiftIR(cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
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/* RUNTEST 49152 TCK; */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(4099645/clk_period);
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_jtag->toggleClk(4099645/_clk_period);
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/* RUNTEST 512 TCK; */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(512);
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@ -148,7 +159,7 @@ void Altera::programMem(RawParser &_bit)
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/* RUNTEST 12000 TCK; */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000000/clk_period);
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_jtag->toggleClk(1000000/_clk_period);
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/* -> idle */
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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}
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@ -214,6 +225,20 @@ void Altera::program(unsigned int offset, bool unprotect_flash)
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{
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if (_mode == Device::NONE_MODE)
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return;
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/* Access clk frequency to store clk_period required
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* for all operations. Can't be done at CTOR because
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* frequency be changed between these 2 methods.
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*
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*/
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_clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
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/* Specific case for MAX10 */
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if (_fpga_family == MAX10_FAMILY) {
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max10_program();
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return;
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}
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/* in all case we consider svf is mandatory
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* MEM_MODE : svf file provided for constructor
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* is the bitstream to use
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@ -264,6 +289,366 @@ uint32_t Altera::idCode()
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((rx_data[3] << 24) & 0xff000000));
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}
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/* MAX 10 specifics methods */
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/* ------------------------ */
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#define MAX10_ISC_ADDRESS_SHIFT {0x03, 0x02}
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#define MAX10_ISC_READ {0x05, 0x02}
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#define MAX10_ISC_ENABLE {0xcc, 0x02}
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#define MAX10_ISC_DISABLE {0x01, 0x02}
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#define MAX10_ISC_ADDRESS_SHIFT {0x03, 0x02}
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#define MAX10_ISC_PROGRAM {0xf4, 0x02}
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#define MAX10_DSM_ICB_PROGRAM {0xF4, 0x03}
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#define MAX10_DSM_VERIFY {0x07, 0x03}
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#define MAX10_DSM_CLEAR {0xf2, 0x03}
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#define MAX10_BYPASS {0xFF, 0x03}
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typedef struct {
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uint32_t dsm_addr;
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uint32_t dsm_len; // 32bits
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uint32_t ufm_addr; // UFM1 addr
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uint32_t ufm_len[2];
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uint32_t cfm_addr; // CFM2 addr
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uint32_t cfm_len[3];
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} max10_mem_t;
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static const std::map<uint32_t, max10_mem_t> max10_memory_map = {
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{0x031820dd, {
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0x0000, 512, // DSM
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0x0200, {4096, 4096}, // UFM
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0x2200, {35840, 14848, 20992}} // CFM
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},
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};
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void Altera::max10_program()
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{
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POFParser _bit(_filename, true);
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_bit.parse();
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_bit.displayHeader();
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uint32_t base_addr; // CFM2 addr
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uint32_t offset = 0;
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auto mem_map = max10_memory_map.find(_idcode);
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if (mem_map == max10_memory_map.end()) {
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printError("Model not supported. Please update max10_memory_map.");
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throw std::runtime_error("Model not supported. Please update max10_memory_map.");
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}
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max10_mem_t mem = mem_map->second;
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const uint8_t *cfm_data = _bit.getData("CFM0");
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const uint8_t *ufm_data = _bit.getData("UFM");
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const uint8_t *dsm_data = _bit.getData("ICB");
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const int dsm_len = _bit.getLength("ICB") / 32; // getLength (bits) dsm_len in 32bits word
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max_10_flow_enable();
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max10_flow_erase();
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max10_dsm_verify();
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/* Write */
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// CFM2->0
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offset = 0;
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base_addr = mem.cfm_addr;
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for (int i = 2; i >= 0; i--) {
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printInfo("Write CFM" + std::to_string(i));
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writeXFM(cfm_data, base_addr, offset, mem.cfm_len[i]);
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base_addr += mem.cfm_len[i];
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offset += (mem.cfm_len[i] * 4);
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}
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// UFM1->0
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offset = 0;
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base_addr = mem.ufm_addr;
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for (int i = 1; i >= 0; i--) {
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printInfo("Write UFM" + std::to_string(i));
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writeXFM(ufm_data, base_addr, offset, mem.ufm_len[i]);
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offset += mem.ufm_len[i] * 4;
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base_addr += mem.ufm_len[i];
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}
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/* Verify */
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if (_verify) {
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// CFM2->0
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offset = 0;
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base_addr = mem.cfm_addr;
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for (int i = 2; i >= 0; i--) {
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printInfo("Verify CFM" + std::to_string(i));
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verifyxFM(cfm_data, base_addr, offset, mem.cfm_len[i]);
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base_addr += mem.cfm_len[i];
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offset += (mem.cfm_len[i] * 4);
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}
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// UFM1->0
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offset = 0;
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base_addr = mem.ufm_addr;
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for (int i = 1; i >= 0; i--) {
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printInfo("Verify UFM" + std::to_string(i));
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verifyxFM(ufm_data, base_addr, offset, mem.ufm_len[i]);
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offset += mem.ufm_len[i] * 4;
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base_addr += mem.ufm_len[i];
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}
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}
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// DSM
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max10_dsm_program(dsm_data, dsm_len);
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max10_dsm_verify();
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max10_flow_program_donebit();
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max10_dsm_verify();
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max10_dsm_program_success();
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max10_dsm_verify();
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/* disable ISC flow */
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max_10_flow_disable();
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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}
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static void word_to_array(uint32_t in, uint8_t *out) {
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out[0] = (in >> 0) & 0xff;
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out[1] = (in >> 8) & 0xff;
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out[2] = (in >> 16) & 0xff;
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out[3] = (in >> 24) & 0xff;
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}
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void Altera::max10_flow_erase()
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{
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const uint32_t dsm_clear_delay = 350000120 / _clk_period;
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const uint8_t dsm_clear[2] = MAX10_DSM_CLEAR;
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max10_addr_shift(0x000000);
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_jtag->shiftIR((unsigned char *)dsm_clear, NULL, IRLENGTH);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(dsm_clear_delay);
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}
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void Altera::writeXFM(const uint8_t *cfg_data, uint32_t base_addr, uint32_t offset, uint32_t len)
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{
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uint8_t *ptr = (uint8_t *)cfg_data + offset; // FIXME: maybe adding offset here ?
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const uint8_t isc_program[2] = MAX10_ISC_PROGRAM;
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/* precompute some delays required during loop */
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const uint32_t isc_program2_delay = 320000 / _clk_period; // ns must be 350us
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ProgressBar progress("Verify", len, 50, _quiet);
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for (uint32_t i = 0; i < len; i+=512) {
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bool must_send_sir = true;
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uint32_t max = (i + 512 <= len)? 512 : len - i;
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for (uint32_t ii = 0; ii < max; ii++) {
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const uint32_t data = ARRAY2INT32(ptr);
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progress.display(i);
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/* flash was erased before: to save time skip write when cfg_data
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* contains only bit set to high
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*/
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if (data == 0xffffffff) {
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must_send_sir = true;
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ptr += 4;
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continue;
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}
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/* TODO: match more or less svf but not bsdl */
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if (must_send_sir) {
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/* Set base addr */
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max10_addr_shift(base_addr + i + ii);
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/* set ISC_PROGRAM/DSM_PROGRAM */
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_jtag->shiftIR((unsigned char *)isc_program, NULL, IRLENGTH, Jtag::PAUSE_IR);
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must_send_sir = false;
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}
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_jtag->shiftDR(ptr, NULL, 32, Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(isc_program2_delay);
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ptr += 4;
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}
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}
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progress.done();
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}
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uint32_t Altera::verifyxFM(const uint8_t *cfg_data, uint32_t base_addr, uint32_t offset,
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uint32_t len)
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{
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uint8_t *ptr = (uint8_t *)cfg_data + offset; // avoid passing offset ?
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//const uint32_t isc_read_delay = 5120 / _clk_period;
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const uint8_t read_cmd[2] = MAX10_ISC_READ;
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uint32_t errors = 0;
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ProgressBar progress("Verify", len, 50, _quiet);
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for (uint32_t i = 0; i < len; i+=512) {
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const uint32_t max = (i + 512 <= len)? 512 : len - i;
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progress.display(i);
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/* send address */
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max10_addr_shift(base_addr + i);
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/* send read command */
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_jtag->shiftIR((unsigned char *)read_cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
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for (uint32_t ii = 0; ii < max; ii++) {
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uint8_t data[4];
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_jtag->shiftDR(NULL, data, 32, Jtag::RUN_TEST_IDLE);
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/* TODO: compare */
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for (uint8_t pos = 0; pos < 4; pos++) {
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if (ptr[pos] != data[pos]) {
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printf("Error@%d: %02x %02x %02x %02x ", pos, data[0], data[1], data[2], data[3]);
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printf("%02x %02x %02x %02x\n", ptr[0], ptr[1], ptr[2], ptr[3]);
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errors++;
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break;
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}
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}
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ptr += 4;
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}
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}
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if (errors == 0)
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progress.done();
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else
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progress.fail();
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return errors;
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}
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void Altera::max_10_flow_enable()
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{
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const int enable_delay = 350000120 / _clk_period; // must be 1 tck
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const uint8_t cmd[2] = MAX10_ISC_ENABLE;
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(enable_delay);
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}
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void Altera::max_10_flow_disable()
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{
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//ISC_DISABLE WAIT 100.0e-3)
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//BYPASS WAIT 305.0e-6
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const int disable_len = (1e9 * 350e-3) / _clk_period;
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const int bypass_len = (3 + (1e9 * 1e-3) / _clk_period);
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const uint8_t cmd0[2] = MAX10_ISC_DISABLE;
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const uint8_t cmd1[2] = MAX10_BYPASS;
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_jtag->shiftIR((unsigned char *)cmd0, NULL, IRLENGTH);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(disable_len);
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_jtag->shiftIR((unsigned char *)cmd1, NULL, IRLENGTH);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(bypass_len);
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}
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void Altera::max10_dsm_program(const uint8_t *dsm_data, const uint32_t dsm_len)
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{
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const int program_del = 5120 / _clk_period;
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const int write_del = 320000 / _clk_period;
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uint32_t *icb_dat = (uint32_t *)dsm_data;
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const int len = dsm_len / 32;
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const uint8_t cmd[2] = MAX10_DSM_ICB_PROGRAM;
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uint8_t dat[4];
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/* Instead of writing the full section
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* only write word with a value != 0xffffffff
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*/
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for (int i = 0; i < len; i++) {
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if (icb_dat[i] != 0xffffffff) {
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/* send addr */
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max10_addr_shift(i);
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word_to_array(icb_dat[i], dat);
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(program_del);
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_jtag->shiftDR(dat, NULL, 32, Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(write_del); // 305.0e-6
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}
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}
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}
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bool Altera::max10_dsm_verify()
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{
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const uint32_t dsm_delay = 5120 / _clk_period;
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const uint8_t cmd[2] = MAX10_DSM_VERIFY;
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const uint8_t tx = 0x00; // 1 in bsdl, 0 in svf
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uint8_t rx=0;
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
|
||||
_jtag->set_state(Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(dsm_delay);
|
||||
_jtag->shiftDR(&tx, &rx, 1, Jtag::RUN_TEST_IDLE);
|
||||
|
||||
printf("BSM: %02x\n", rx);
|
||||
if ((rx & 0x01) == 0x01) {
|
||||
printInfo("DSM Verify: OK");
|
||||
return true;
|
||||
}
|
||||
printError("DSM Verify: KO");
|
||||
return false;
|
||||
}
|
||||
|
||||
void Altera::max10_addr_shift(uint32_t addr)
|
||||
{
|
||||
const uint8_t cmd[2] = MAX10_ISC_ADDRESS_SHIFT;
|
||||
const uint32_t base_addr = POFParser::reverse_32(addr) >> 9;
|
||||
|
||||
uint8_t addr_arr[4];
|
||||
word_to_array(base_addr, addr_arr);
|
||||
//printf("%08x %08x\n", addr, base_addr);
|
||||
|
||||
/* FIXME/TODO:
|
||||
* 1. in bsdl file no delay between IR and DR
|
||||
* but 1TCK after DR
|
||||
* 2. PAUSE IR is a state where loop is possible -> required to move
|
||||
* to RUN_TEST_IDLE ?
|
||||
*/
|
||||
_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
|
||||
_jtag->set_state(Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(5120 / _clk_period); // fine delay ?
|
||||
_jtag->shiftDR(addr_arr, NULL, 23, Jtag::RUN_TEST_IDLE);
|
||||
}
|
||||
|
||||
void Altera::max10_dsm_program_success()
|
||||
{
|
||||
const uint32_t prog_len = 5120 / _clk_period; // ??
|
||||
const uint32_t prog2_len = 320000 / _clk_period; // ??
|
||||
//
|
||||
const uint8_t cmd[2] = MAX10_DSM_ICB_PROGRAM;
|
||||
|
||||
uint8_t magic[4];
|
||||
word_to_array(0x6C48A50F, magic); // FIXME: uses define instead
|
||||
|
||||
max10_addr_shift(0x00000b);
|
||||
|
||||
/* Send 'Magic' code */
|
||||
_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
|
||||
_jtag->set_state(Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(prog_len); // fine delay ?
|
||||
_jtag->shiftDR(magic, NULL, 32, Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(prog2_len); // must wait 305.0e-6
|
||||
}
|
||||
|
||||
void Altera::max10_flow_program_donebit()
|
||||
{
|
||||
const uint32_t addr_shift_delay = 5120 / _clk_period; // ??
|
||||
const uint32_t icb_program_delay = 320000 / _clk_period; // ??
|
||||
|
||||
uint8_t cmd[2] = MAX10_DSM_ICB_PROGRAM;
|
||||
|
||||
uint8_t magic[4];
|
||||
word_to_array(0x6C48A50F, magic); // FIXME: uses define instead
|
||||
|
||||
/* Send target address */
|
||||
max10_addr_shift(0x000009);
|
||||
|
||||
/* Send 'Magic' code */
|
||||
_jtag->shiftIR(cmd, NULL, IRLENGTH, Jtag::PAUSE_IR);
|
||||
_jtag->set_state(Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(addr_shift_delay); // fine delay ?
|
||||
_jtag->shiftDR(magic, NULL, 32, Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(icb_program_delay); // must wait 305.0e-6
|
||||
}
|
||||
|
||||
/* SPI interface */
|
||||
|
||||
int Altera::spi_put(uint8_t cmd, const uint8_t *tx, uint8_t *rx, uint32_t len)
|
||||
|
|
@ -291,6 +676,7 @@ int Altera::spi_put(uint8_t cmd, const uint8_t *tx, uint8_t *rx, uint32_t len)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int Altera::spi_put(const uint8_t *tx, uint8_t *rx, uint32_t len)
|
||||
{
|
||||
return spi_put(tx[0], &tx[1], rx, len-1);
|
||||
|
|
|
|||
|
|
@ -82,6 +82,31 @@ class Altera: public Device, SPIInterface {
|
|||
bool post_flash_access() override;
|
||||
|
||||
private:
|
||||
enum altera_family_t {
|
||||
MAX2_FAMILY = 0,
|
||||
MAX10_FAMILY = 1,
|
||||
CYCLONE5_FAMILY = 2,
|
||||
CYCLONE10_FAMILY = 3,
|
||||
STRATIXV_FAMILY = 3,
|
||||
CYCLONE_MISC = 10, // Fixme: idcode shared
|
||||
UNKNOWN_FAMILY = 999
|
||||
};
|
||||
/*************************/
|
||||
/* max10 specific */
|
||||
/*************************/
|
||||
void max10_program();
|
||||
void writeXFM(const uint8_t *cfg_data, uint32_t base_addr, uint32_t offset, uint32_t len);
|
||||
uint32_t verifyxFM(const uint8_t *cfg_data, uint32_t base_addr, uint32_t offset,
|
||||
uint32_t len);
|
||||
void max10_dsm_program_success();
|
||||
void max10_flow_program_donebit();
|
||||
void max10_addr_shift(uint32_t addr);
|
||||
void max_10_flow_enable();
|
||||
void max_10_flow_disable();
|
||||
void max10_flow_erase();
|
||||
void max10_dsm_program(const uint8_t *dsm_data, const uint32_t dsm_len);
|
||||
bool max10_dsm_verify();
|
||||
|
||||
/*!
|
||||
* \brief with intel devices SPI flash direct access is not possible
|
||||
* so a bridge must be loaded in RAM to access flash
|
||||
|
|
@ -110,6 +135,10 @@ class Altera: public Device, SPIInterface {
|
|||
std::string _spiOverJtagPath; /**< spiOverJtag explicit path */
|
||||
uint32_t _vir_addr; /**< addr affected to virtual jtag */
|
||||
uint32_t _vir_length; /**< length of virtual jtag IR */
|
||||
uint32_t _clk_period; /**< JTAG clock period */
|
||||
|
||||
altera_family_t _fpga_family;
|
||||
uint32_t _idcode;
|
||||
};
|
||||
|
||||
#endif // SRC_ALTERA_HPP_
|
||||
|
|
|
|||
Loading…
Reference in New Issue