2021-04-19 21:17:08 +02:00
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|
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set parts [lindex $argv 0]
|
2019-10-05 19:03:28 +02:00
|
|
|
|
2020-08-08 11:42:38 +02:00
|
|
|
set project_name "spiOverJtag"
|
2019-10-05 19:03:28 +02:00
|
|
|
|
2021-04-19 21:17:08 +02:00
|
|
|
set build_path tmp_${parts}
|
2019-10-05 19:03:28 +02:00
|
|
|
file delete -force $build_path
|
|
|
|
|
|
|
|
|
|
# Project creation
|
2021-04-19 21:17:08 +02:00
|
|
|
set grade [dict create \
|
2021-04-20 21:28:14 +02:00
|
|
|
xc7a35tcpg236 -1 \
|
2021-04-19 21:17:08 +02:00
|
|
|
xc7a35tcsg324 -1 \
|
|
|
|
|
xc7a35tftg256 -1 \
|
|
|
|
|
xc7a50tcpg236 -2 \
|
|
|
|
|
xc7a75tfgg484 -2 \
|
|
|
|
|
xc7a100tfgg484 -2 \
|
|
|
|
|
xc7a200tsbg484 -1 \
|
2022-02-19 03:33:32 +01:00
|
|
|
xc7k325tffg676 -1 \
|
2022-02-22 18:01:02 +01:00
|
|
|
xc7k325tffg900 -2 \
|
2022-09-30 11:01:49 +02:00
|
|
|
xc7s25csga225 -1 \
|
2021-04-19 21:17:08 +02:00
|
|
|
xc7s50csga324 -1 \
|
2020-10-15 16:07:55 +02:00
|
|
|
]
|
2021-04-19 21:17:08 +02:00
|
|
|
|
|
|
|
|
set pkg_name [dict create \
|
2021-04-20 21:28:14 +02:00
|
|
|
xc7a35tcpg236 xc7a_cpg236 \
|
2021-04-19 21:17:08 +02:00
|
|
|
xc7a35tcsg324 xc7a_csg324 \
|
|
|
|
|
xc7a35tftg256 xc7a_ftg256 \
|
|
|
|
|
xc7a50tcpg236 xc7a_cpg236 \
|
|
|
|
|
xc7a75tfgg484 xc7a_fgg484 \
|
|
|
|
|
xc7a100tfgg484 xc7a_fgg484 \
|
|
|
|
|
xc7a200tsbg484 xc7a_sbg484 \
|
|
|
|
|
xc7a200tfbg484 xc7a_fbg484 \
|
2022-02-19 03:33:32 +01:00
|
|
|
xc7k325tffg676 xc7k_ffg676 \
|
2022-02-22 18:01:02 +01:00
|
|
|
xc7k325tffg900 xc7k_ffg900 \
|
2022-09-30 11:01:49 +02:00
|
|
|
xc7s25csga225 xc7s_csga225 \
|
2021-04-19 21:17:08 +02:00
|
|
|
xc7s50csga324 xc7s_csga324 \
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
set curr_grade [dict get $grade $parts]
|
|
|
|
|
set curr_pins [dict get $pkg_name $parts]
|
|
|
|
|
|
|
|
|
|
create_project $project_name $build_path -part ${parts}${curr_grade}
|
2019-10-05 19:03:28 +02:00
|
|
|
|
|
|
|
|
add_files -norecurse xilinx_spiOverJtag.vhd
|
2021-04-19 21:17:08 +02:00
|
|
|
add_files -norecurse -fileset constrs_1 constr_${curr_pins}.xdc
|
2019-10-05 19:03:28 +02:00
|
|
|
|
|
|
|
|
set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset]
|
|
|
|
|
|
|
|
|
|
# set the current synth run
|
|
|
|
|
current_run -synthesis [get_runs synth_1]
|
|
|
|
|
reset_run synth_1
|
|
|
|
|
|
|
|
|
|
set obj [get_runs impl_1]
|
|
|
|
|
set_property AUTO_INCREMENTAL_CHECKPOINT 1 [get_runs impl_1]
|
|
|
|
|
|
|
|
|
|
set_property "needs_refresh" "1" $obj
|
|
|
|
|
|
|
|
|
|
# set the current impl run
|
|
|
|
|
current_run -implementation [get_runs impl_1]
|
|
|
|
|
|
|
|
|
|
puts "INFO: Project created: $project_name"
|
|
|
|
|
|
|
|
|
|
launch_runs synth_1 -jobs 4
|
|
|
|
|
wait_on_run synth_1
|
|
|
|
|
## do implementation
|
|
|
|
|
launch_runs impl_1 -jobs 4
|
|
|
|
|
wait_on_run impl_1
|
|
|
|
|
## make bit file
|
|
|
|
|
launch_runs impl_1 -jobs 4 -to_step write_bitstream
|
|
|
|
|
wait_on_run impl_1
|
|
|
|
|
exit
|
