39 lines
905 B
Tcl
39 lines
905 B
Tcl
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set model [lindex $argv 0]
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set project_name "spiOverJtag_${model}"
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set build_path tmp
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file delete -force $build_path
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# Project creation
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create_project $project_name $build_path -part xc7a35ticsg324-1L
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add_files -norecurse xilinx_spiOverJtag.vhd
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add_files -norecurse -fileset constrs_1 constr.xdc
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set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset]
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# set the current synth run
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current_run -synthesis [get_runs synth_1]
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reset_run synth_1
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set obj [get_runs impl_1]
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set_property AUTO_INCREMENTAL_CHECKPOINT 1 [get_runs impl_1]
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set_property "needs_refresh" "1" $obj
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# set the current impl run
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current_run -implementation [get_runs impl_1]
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puts "INFO: Project created: $project_name"
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launch_runs synth_1 -jobs 4
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wait_on_run synth_1
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## do implementation
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launch_runs impl_1 -jobs 4
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wait_on_run impl_1
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## make bit file
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launch_runs impl_1 -jobs 4 -to_step write_bitstream
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wait_on_run impl_1
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exit
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