6ec6e1c723
Add optional series resistance or junction capacitance, if non
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is defined in the .model statement. This may help achieving
convergence if subcircut models of opamps etc use simple diodes
as voltage limiters. Example call:
.options diode_cj0=20p diode_rser=20m
2024-09-23 12:34:17 +02:00
b14420803a
Fix commit 09685dde1
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("Set lower case for variables or vectors in command 'echo'.
Tokens starting with '$' will get lower-casing.", 2024-09-07)
Don't use s as name for temporary string, as s has been set
already and is used later.
2024-09-13 11:35:28 +02:00
09685dde1c
Set lower case for variables or vectors in command 'echo'.
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Tokens starting with '$' will get lower-casing.
2024-09-07 18:50:13 +02:00
02a5f6691e
Fixed KLU conversion to complex for SP Analysis
2024-08-29 00:24:58 +02:00
ecc8990e20
Make error messages more verbose:
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add line number and source file name.
2024-08-28 16:20:10 +02:00
30ee6dff97
Add line number and source file to some error messages
2024-08-28 16:08:36 +02:00
0553960e37
Fix warning message
2024-08-28 16:05:56 +02:00
a3bae9bc7a
More on verbose error and warning messages
2024-08-28 16:05:03 +02:00
d18680d728
Allow KiCad special token V(/xyz) by quoting
2024-08-28 15:14:00 +02:00
ce656bd400
Make error messages more verbose:
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add line number and source file name.
2024-08-28 15:12:56 +02:00
4a9a734bf3
Fix bug #680 . Check that src/dest memcpy arguments are non-NULL.
2024-08-23 19:52:30 +02:00
4b0beff839
extend bsim4 operating point info list
2024-08-23 09:14:31 +02:00
4a8000cad9
Add simulator version info to raw file ('write' commad)
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using an extra line 'Command: ...').
The old sequence (adding commands manually to raw file) is
still available.
The 'Command: anycommand' will not be executed if loading
an ngspice-generated raw file. Raw files from other simulators may
generate a warning that the command is not available.
2024-08-18 14:21:03 +02:00
413382bd56
Add simulator version info to raw file in batch mode,
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using the line 'Command:...'
2024-08-18 14:16:42 +02:00
b03dd90694
Fix #686 : "XSpice Verilog Vector Input Bug".
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Bug report and fix by Aodhan Murray.
2024-08-16 12:25:30 +02:00
816f43dd36
Improve debugging using shared ngspice:
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print out each command received.
2024-08-16 12:21:12 +02:00
6ea6f8d9a8
Add a comment
2024-08-03 16:08:41 +02:00
ee9a8462ea
add missing klu bindings
2024-08-02 16:32:47 +02:00
3af65f1d28
Notes go to stdout.
2024-08-01 13:39:18 +02:00
7bfaefada4
Don't dereference a NULL pointer.
2024-08-01 13:36:44 +02:00
f95e8c2e3a
Error and warning messages to stderr
2024-08-01 13:28:32 +02:00
2e8bd0cea6
Note directed to stdout
2024-08-01 13:28:08 +02:00
c2795a350a
enable compiling with CYGWIN
2024-07-26 12:08:51 +02:00
038c18429f
Fix gcc warnings.
2024-07-25 21:33:44 +02:00
beb07ea6df
Add a utility function to the d_cosim code model to open dynamic
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libraries. It automatically tries adding standard file extensions,
so that model lines for d_cosim can be the same for all OSs.
2024-07-25 21:33:16 +02:00
cdbe31868f
Add support for including Verilog simulation within an instance
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of the d_cosim codemodel, using libvvp, the simulation runtime of
Icarus Verilog. This complements the existing method using Verilator.
The new source code is built into two binary shared libraries,
ivlng.so (or .DLL) and ivlng.vpi that are loaded during simulation.
2024-07-25 21:32:59 +02:00
e201f144d5
Add support for Verilator's --timing option, allowing use of delays
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in Verilog source code. Also add two parameters to d_cosim:
sim_args is used to pass string arguments to a Verilator simulation;
and lib_args is for future use. In vlnggen, also check for two causes
of failure: a verilator error may lead to creation of interfering header
files; and misleading instances of verilated_shim.cpp can cause an obscure
failure (reported by Diarmuid Collins).
Use a generic name for the generated DLL in MSVC.CMD.
2024-07-25 21:32:42 +02:00
4481531baf
Allow trailing null connections to be omitted from XSPICE device
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lines. Also tidy some code,
2024-07-25 21:32:21 +02:00
ab1f16517e
Changes to d_cosim to work with initial support for Icarus Verilog.
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Fully resolve symbols on loading and tolerate attempts to set
output in the past.
2024-07-25 21:31:46 +02:00
aa9a0a637e
vbic: have to load Vrxf/Itxf with value
2024-07-23 14:34:32 +02:00
bf020ca173
vbic: correct op reporting for excess phase model
2024-07-23 10:50:19 +02:00
31dba308d6
Merge branch 'pre-master-44' of ssh://git.code.sf.net/p/ngspice/ngspice into pre-master-44
2024-07-20 17:55:27 +02:00
f0ff8b230b
Remove sourceinfo upon shared ngspice reset.
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Remove memory leaks.
2024-07-20 17:54:43 +02:00
cbca05cd6b
format: rm misleading indentation
2024-07-20 16:09:39 +02:00
272e4cc6fb
Memcpy only when p_word is not NULL
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enable -fsanitize=address
2024-07-16 17:01:57 +02:00
98479267d4
Revert "memcpy only if p_word is not NULL"
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This reverts commit 58787756d4
2024-07-16 16:48:23 +02:00
a43c6f4916
Add #define RESMIN 1e-6 as a minimum resistor value
2024-07-16 16:25:54 +02:00
0ac18a37c0
Stop the worker thread when running
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Delete mutexes only after all other resets and delets.
2024-07-16 16:22:07 +02:00
c61fc35231
Set pl_lookup_table to NULL after freeing: allow another initialization
2024-07-16 16:21:53 +02:00
07b10bc1a1
Bail out when state file is not found.
2024-07-16 16:21:44 +02:00
d2cc17b45d
Add function ngSpice_Reset(void) to completely reset shared ngspice,
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so that it may be restartet again by ngSpice_Init
2024-07-16 16:21:36 +02:00
620b9c86ce
Update copyright
2024-07-16 16:21:22 +02:00
58787756d4
memcpy only if p_word is not NULL
2024-07-16 16:06:54 +02:00
0721afc355
Merge /u/mtasaka/ngspice/ branch asan-segv-fix into pre-master-44
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https://sourceforge.net/p/ngspice/ngspice/merge-requests/19/
2024-07-16 07:35:20 +00:00
38f6bbe5ec
misc/string.c: fix one byte ahead access in dup_string
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In dup_string in misc/string.c , even if the destination
buffer is allocated with n_char bytes,
the source buffer `str` can be accessed up to only n_char bytes.
2024-07-16 15:52:09 +09:00
942b4f62b4
43+ developing towards ngspice-44
2024-07-14 12:58:45 +02:00
2af390f0b1
Update copyright info
2024-07-13 10:14:02 +02:00
08d834841f
diode: init of potential uninitialized variable
2024-07-12 14:26:53 +02:00
4ad7d10aef
init of potential uninitialized variables
2024-07-12 14:26:44 +02:00
bbfb3953ed
repair missing parenthesis
2024-07-12 14:26:33 +02:00
Holger Vogt
Francesco Lannutti
Brian Taylor
Matthias Schweikardt
Giles Atkinson
dwarning
Vogt
b'Holger Vogt
Mamoru TASAKA