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Fix #686: "XSpice Verilog Vector Input Bug".

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Bug report and fix by Aodhan Murray.
This commit is contained in:
Giles Atkinson
2024-08-16 12:25:30 +02:00
committed by Holger Vogt
parent 816f43dd36
commit b03dd90694
1 changed files with 27 additions and 27 deletions
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src/xspice/verilog/verilator_shim.cpp
+27 -27
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@@ -40,18 +40,18 @@ static unsigned char previous_output[outs + inouts];
/* The input function: it should ignore out-of-range values of index. */
#define VL_DATA(size, name, msb, lsb) \
if (index >= msb - lsb + 1) { \
index -= msb - lsb + 1; \
} else if (msb == 0 && lsb == 0) { \
topp->name = val ? 1 : 0; \
return; \
} else { \
if (val) \
topp->name |= (1 << (msb - index)); \
else \
topp->name &= (1 << (msb - index)); \
return; \
#define VL_DATA(size, name, msb, lsb) \
if (index >= msb - lsb + 1) { \
index -= msb - lsb + 1; \
} else if (msb == 0 && lsb == 0) { \
topp->name = val ? 1 : 0; \
return; \
} else { \
if (val) \
topp->name |= (1 << (msb - index)); \
else \
topp->name &= ~(1 << (msb - index)); \
return; \
}
static void accept_input(struct co_info *pinfo,
@@ -70,21 +70,21 @@ static void accept_input(struct co_info *pinfo,
offset = outs;
#undef VL_DATA
#define VL_DATA(size, name, msb, lsb) \
if (index >= msb - lsb + 1) { \
index -= msb - lsb + 1; \
offset += msb - lsb + 1; \
} else if (msb == 0 && lsb == 0) { \
topp->name = val ? 1 : 0; \
previous_output[index + offset] = val; \
return; \
} else { \
if (val) \
topp->name | (1 << (msb - index)); \
else \
topp->name &= (1 << (msb - index)); \
previous_output[index + offset] = val; \
return; \
#define VL_DATA(size, name, msb, lsb) \
if (index >= msb - lsb + 1) { \
index -= msb - lsb + 1; \
offset += msb - lsb + 1; \
} else if (msb == 0 && lsb == 0) { \
topp->name = val ? 1 : 0; \
previous_output[index + offset] = val; \
return; \
} else { \
if (val) \
topp->name | (1 << (msb - index)); \
else \
topp->name &= ~(1 << (msb - index)); \
previous_output[index + offset] = val; \
return; \
}
#include "inouts.h"