Commit Graph

366 Commits

Author SHA1 Message Date
Holger Vogt d7bdfe1a20 Re-add optional selection of Berkeley model parameters. 2022-12-19 12:43:55 +01:00
h_vogt 5ec6543dbb Add log plots
Add sim vs. Temp.
Add y-labels
2022-12-19 12:43:27 +01:00
Holger Vogt e28d3feee0 Remove unused variable debarr.
Add another example.
2022-12-11 15:39:10 +01:00
Holger Vogt 45574cecb2 derivative inside of .func 2022-12-11 15:38:49 +01:00
Holger Vogt 89a48e7d73 simple example for derivative in B source 2022-12-11 15:38:37 +01:00
Holger Vogt 082ae1603e add linewidth for graphs 2022-12-11 15:36:57 +01:00
Holger Vogt 058e7a34f8 tiny update, typos, font size 2022-12-11 15:36:42 +01:00
Brian Taylor 7ff8f3773f Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 2022-12-11 15:34:33 +01:00
Brian Taylor cd883d23d6 Examples for 74*568 behavioral subckts. 2022-12-11 15:33:53 +01:00
Holger Vogt 5324319edb Move digital examples to new locations 2022-12-11 15:33:08 +01:00
Holger Vogt 925dc55a73 rename example file 2022-12-11 15:28:23 +01:00
Holger Vogt ca1974ff37 Examples moved to folder /various 2022-12-11 15:28:01 +01:00
Holger Vogt 751019b447 Examples for d_pwm and d_osc 2022-12-11 15:27:42 +01:00
Brian Taylor 4294f49968 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented. 2022-12-11 15:25:24 +01:00
Brian Taylor d425beb557 Typo, 2 x1 subcircuits. 2022-12-11 15:20:49 +01:00
Brian Taylor d54c1fc091 Add pindly tristate example. Cleanup error handling. 2022-12-11 15:20:27 +01:00
Brian Taylor b142be7fde Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE. 2022-12-11 15:19:39 +01:00
Brian Taylor 4e76586b6b Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly. 2022-12-11 15:19:17 +01:00
Holger Vogt 43de22ec24 Update to the examples: enable plotting with option digitop 2022-10-24 17:05:34 +02:00
Holger Vogt 0aff89dc28 Example for URC distributed RC transmission line 2022-10-22 16:00:15 +02:00
Holger Vogt ec6a902fb9 Fix a bug in simple diode, when ilimit is set, but not epsilon.
Make model more similar to LTSPICE
Add an example
2022-10-08 16:50:38 +02:00
Giles Atkinson b212a49982 Add some automatic bridge examples, mostly using the bidirectional bridge. 2022-10-08 16:48:36 +02:00
Holger Vogt cb42895dad example for pwlts source code model 2022-10-07 13:39:33 +02:00
Holger Vogt d39c60542d Enable power measurement for W switch 2022-10-07 13:18:51 +02:00
Holger Vogt fe8eb26aaf Replace end-of-line comment delimiter $ by ;
So to make it independent from compatibility switch selection.
2022-10-07 13:18:29 +02:00
Holger Vogt f1eb8d3955 examples for .probe alli or .probe i(xx) 2022-10-07 13:17:55 +02:00
Holger Vogt 3dbfc934bb set colors for grids and data 2022-10-07 13:17:06 +02:00
Brian Taylor 4706c3dea5 Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test. 2022-10-07 13:15:23 +02:00
Holger Vogt e9b5a9a957 aswitch needs two input nodes because gd has been selected for input. 2022-10-07 13:13:38 +02:00
Holger Vogt c8ed9590b7 Handle the case when control voltages on and off are equal.
Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
2022-10-07 13:12:56 +02:00
Holger Vogt 5b0b328186 If a node name to be plotted ends by ':power', its type is set to POWER.
Thus 'settype power nodename(s)' in the examples is no longer necessary.
2022-10-07 13:12:04 +02:00
Holger Vogt 2deefe1fbc New tables for MOS devices 2022-10-07 13:11:18 +02:00
Holger Vogt 765d2e8a0e Return data to input directory. 2022-10-07 13:10:51 +02:00
Holger Vogt a69dd1bcde Simplify the NMOS or PMOS selection by setting only one parameter
'mostype'
ngspice-37+ is required.
2022-10-07 13:10:06 +02:00
Brian Taylor 7f38ce4ebb Remove debug code. 2022-10-07 12:55:42 +02:00
Brian Taylor 112e47d0d3 This test is equivalent to examples/xspice/xspice_c3.cir and uses Pspice subckts for the divider and nand gate. 2022-10-07 12:53:03 +02:00
Brian Taylor e8dfd16cb2 Add counter test. Check for usage of $d_lo, $d_hi, $d_nc usage with dff, jkff, dltch which will not translate to Xspice. 2022-10-07 12:52:39 +02:00
Brian Taylor f7c519f149 All-digital U* device examples. No a/d or d/a interfaces on the subcircuits. 2022-10-07 12:52:20 +02:00
Holger Vogt c4efe2e3ac Update, link on device models (public domain or TI)
Download adresses for TI models.
2022-05-15 18:36:35 +02:00
Giles Atkinson 2e329986b8 Fix filename case. 2022-05-10 15:29:51 +02:00
Holger Vogt ac8f8ad65d New example: S-parameters of a Tschebyschef Low Pass filter 2022-05-09 10:07:48 +02:00
Holger Vogt 07feb637b5 New example for power measurement with .probe 2022-05-09 10:07:41 +02:00
Holger Vogt 129893b399 S-parameters: Replace S11 by S_1_1 etc. to avoid ambiguity
when more than 10 ports are measured.
Update to S-parameter script and command wr2sp
2022-04-29 07:29:14 +02:00
Holger Vogt aca85ec386 Add .probe p(...) commands (including plotting and averaging) 2022-04-26 10:37:10 +02:00
Holger Vogt cd451bd5b3 Add measuring power of the VDMOS devices with .probe p(device) 2022-04-26 10:36:39 +02:00
Holger Vogt a0ee275b08 Improve printout formatting 2022-04-26 10:33:01 +02:00
Holger Vogt 6b03aaa15f examples for loops.
The syntax is listed in the ngspice manual,
chapter 17.6 Control Structures. Practical examples
using a simple voltage divider circuit are given here.
2022-04-26 10:32:53 +02:00
Holger Vogt 9882c3a24c New examples: command 'sp' and three-port example 2022-04-25 21:31:58 +02:00
Holger Vogt 5fb19c41bc Fix internet address 2022-04-25 21:30:07 +02:00
Holger Vogt a3d55cdddb Replace (all) by alli 2022-04-25 21:29:55 +02:00