Commit Graph

8074 Commits

Author SHA1 Message Date
Pascal Kuthe acfaf023b3 prototype for Verilog-A integration using OSDI and OpenVAF
This initial prototype is capable of performing DC, transient and AC
analysis. Not all features of OSDI are supported yet and there are still
some open questions regarding ngspice integration. However many usecase
already work very well and a large amount of CMC models are supported.
The biggest missing feature right now is noise analysis.

test: test case for diode DC working with SH

test: add transient analysis to osdi_diode test

test: added docu text to osdi_diode test

test: added test case directories

fix: bug in osdi_load

test: small change to netlist

fix: implement DEVunsetup

fix: correct behaviour for MODEINITSMSIG

test: osdi diode enable all analysis modes

removed netlist

ignoring test results

added the build of the diode shared object to the python test script

deleting old stuff and always rebuilding the shared object

added diode_va.c to the repo

preparing CI

Create .gitlab-ci.yml file

(testing) add res, cap and multiple devices test

feat: use osdi command to load files

Previously OSDI shared object files were loaded from fixed directories.
This was unreliable, inconvenient and caused conflicts with XSPICE.

This commit remove the old loading mechanism and instead introduces the
`osdi` command that can load (a list of) osdi object files (like the
codemodel command for XSPICE). A typical usecase will use this as a
precommand in the netlist:

.control
pre_osdi foo.osdi
.endc

If the specified file is a relative path it is first resolved relative
to the parent directory of the netlist. If the osdi command is invoked
from the interactive prompt the file is resolved relative to the current
working directory instead.

This commit also moves osdi from the devices folder to the root src
folder like xspice. This better reflects the role of the code as users
may otherthwise (mistakenly) assume that osdi is just another
handwritten model.

test: update tests to new command

fix: do not ignore first parameter

feat: implement log message callback

fix: don't generate ddt matrix/rhs in DC sweep

fix: missing linker script

update to osdi 0.3

(testing) simplify test cases, fix bug

(testing) multiple devices test improvement

(testig) node collapsing bugfix

test: increase tolerance in tests

feat: update to newest OSDI header

fix: temperature update dt behaviour

fix: ignored models

fix: compilation script

fix: allow hicum/l2 to compile with older c++ compilers

fix: set required compiler flags for osdi

fix: disable x by default

fix: add missing SPICE functions

fix: update diode to latest ngspice version

feat: implement python CMC test runner

doc: Add README_OSDI.md

fix: make testing script work with python version before 3.9

fix: free of undefined local variable

fix: do not calculate time derivative during tran op

update osdi version

fixes for compilation on windows
2022-12-27 13:51:57 +01:00
Holger Vogt d7bdfe1a20 Re-add optional selection of Berkeley model parameters. 2022-12-19 12:43:55 +01:00
h_vogt 5ec6543dbb Add log plots
Add sim vs. Temp.
Add y-labels
2022-12-19 12:43:27 +01:00
Brian Taylor 0805856fb7 Distinguish between set/reset delays when possible. 2022-12-19 12:43:00 +01:00
Brian Taylor 253df17949 Make it optional to use zl/zh/lz/hz delays for utgate. 2022-12-19 12:42:36 +01:00
Brian Taylor 4c457a3cd4 Avoid unnecessary calculations for utgate. 2022-12-19 12:42:06 +01:00
Brian Taylor a4b609fb6a For utgate timing models, if hl/lh are not present use zl/zh/lz/hz to give a more accurate tristate delay. 2022-12-19 12:41:18 +01:00
Brian Taylor 021982799e More conservative delay estimates for timing model type ugff. 2022-12-19 12:40:50 +01:00
Brian Taylor 11f6eace68 For dff/jkff, obtain more conservative estimates for clk_delay, set_delay and reset_delay. 2022-12-19 12:40:06 +01:00
Holger Vogt cc8b651562 re-enable making old app nutmeg 2022-12-11 15:47:22 +01:00
Holger Vogt d4fcef9bf6 Repair the broken --enable-oldapps option 2022-12-11 15:47:05 +01:00
Holger Vogt 8d9f69f7bf Add --enable-shortcheck as configure option 2022-12-11 15:46:27 +01:00
Holger Vogt e28d3feee0 Remove unused variable debarr.
Add another example.
2022-12-11 15:39:10 +01:00
Holger Vogt 45574cecb2 derivative inside of .func 2022-12-11 15:38:49 +01:00
Holger Vogt 89a48e7d73 simple example for derivative in B source 2022-12-11 15:38:37 +01:00
Holger Vogt 6c1be283a7 Add a function ddt (derivative versus time) to the B-source funtion parser. 2022-12-11 15:38:22 +01:00
Brian Taylor 47260e2eb8 Rewrite extract_model_param. 2022-12-11 15:38:08 +01:00
Brian Taylor 0924fbb7eb Modify the delay calculation for non-conforming timing model in .subckt CD4572UB. 2022-12-11 15:37:34 +01:00
Holger Vogt a5eaac128a For monotonic plotting find out the majority of increasing or decreasing
x-axis values, add a warning to add 'retraceplot' to plot all if more than
10% of the values deviate from the majority.
2022-12-11 15:37:14 +01:00
Holger Vogt 082ae1603e add linewidth for graphs 2022-12-11 15:36:57 +01:00
Holger Vogt 058e7a34f8 tiny update, typos, font size 2022-12-11 15:36:42 +01:00
Holger Vogt 9613625840 Prevent seg fault after strange input like
*no circuit
.save all
.probe alli
.op
.end
2022-12-11 15:36:22 +01:00
Pascal Kuthe 744002dc49 fix sigfault on older c compilers 2022-12-11 15:35:53 +01:00
Giles Atkinson 7ead974a5a Prevent crash when cm_analog_set_temp_bkpt() is called during OPtran(). 2022-12-11 15:35:31 +01:00
Giles Atkinson 73e8fed0fc Fix warnings from gcc 10.2.1. 2022-12-11 15:35:14 +01:00
Brian Taylor 929d1f5190 Added xor/xnor for logicexp timing models. 2022-12-11 15:34:56 +01:00
Brian Taylor 7ff8f3773f Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 2022-12-11 15:34:33 +01:00
Brian Taylor cd883d23d6 Examples for 74*568 behavioral subckts. 2022-12-11 15:33:53 +01:00
Brian Taylor a0cf65ca1a Add B-source note 2022-12-11 15:33:24 +01:00
Holger Vogt 5324319edb Move digital examples to new locations 2022-12-11 15:33:08 +01:00
Holger Vogt 631ff35c34 The 8th parameter on a voltage or current source now is 'number of pulses'.
Previous usage had been PHASE, introduced by XSPICE, which has
been redundant to DELAY. PHASE is again available when compatibility flag
xs has been set.
2022-12-11 15:32:51 +01:00
Holger Vogt e967b31c94 Add a new compatibility mode xs (for XSPICE) 2022-12-11 15:32:30 +01:00
Holger Vogt 27fb6cd0a6 Allow resetting the limit for warning mesaages, when a new run is started. 2022-12-11 15:32:11 +01:00
Holger Vogt 8e175f1e77 Replace obscure warning "singular matrix: check nodes mymode1 and mynode1" by
"singular matrix: check node mynode1", if both node names are equal.
2022-12-11 15:31:41 +01:00
Brian Taylor 1511214874 Add more debug instrumentation. 2022-12-11 15:31:09 +01:00
Brian Taylor fe733a8ca2 Use tilde '~' inputs instead of creating inverters. 2022-12-11 15:30:41 +01:00
Holger Vogt 59e28ac2a2 Remove mentioning line number 0, which has been incomprehensible. 2022-12-11 15:30:12 +01:00
Holger Vogt 59413a7f71 Add error messages when controlled_exit is called:
No exit without message.
2022-12-11 15:29:47 +01:00
Pascal Kuthe 75c2a3c621 calculate log frequency sweep such that start frequency and stop frequency are always exactly included 2022-12-11 15:29:19 +01:00
Pascal Kuthe c5d5da15ee fix: allow hicum/l2 to compile with older c++ compilers 2022-12-11 15:28:59 +01:00
Holger Vogt 925dc55a73 rename example file 2022-12-11 15:28:23 +01:00
Holger Vogt ca1974ff37 Examples moved to folder /various 2022-12-11 15:28:01 +01:00
Holger Vogt 751019b447 Examples for d_pwm and d_osc 2022-12-11 15:27:42 +01:00
Holger Vogt f13aa89626 Add new functions for operators x**y or x^y
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
2022-12-11 15:27:26 +01:00
Holger Vogt d0f686727d Add new functions for operators x**y or x^y
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
2022-12-11 15:27:02 +01:00
Brian Taylor 9932a78e39 Add safety braces. 2022-12-11 15:26:42 +01:00
Brian Taylor 5726c9ff0b Tidy up debug tracing code. 2022-12-11 15:26:16 +01:00
Brian Taylor aa2f3b7bbb Fix memory leaks. 2022-12-11 15:25:52 +01:00
Brian Taylor 4294f49968 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented. 2022-12-11 15:25:24 +01:00
Brian Taylor cefa6b380c When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary. 2022-12-11 15:25:00 +01:00