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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.

This commit is contained in:
Brian Taylor 2022-10-31 17:44:07 -07:00 committed by Holger Vogt
parent 13c01abf0d
commit 4e76586b6b
5 changed files with 141 additions and 13 deletions
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80
examples/p-to-n-examples/decoder.cir Normal file
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@ -0,0 +1,80 @@
decoder,cir
*
* ----------------------------------------------------------- 74145 ------
* BCD-To-Decimal Decoders/Drivers
*
* The TTL Logic Data Book, 1988, TI Pages 2-447 to 2-449
* bss 3/17/94
*
.SUBCKT 74145 A B C D O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+ optional: DPWR=$G_DPWR DGND=$G_DGND
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(4,10) DPWR DGND
+ A B C D
+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+ D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+ abar = {~A}
+ bbar = {~B}
+ cbar = {~C}
+ dbar = {~D}
+ O0_O = {~(abar & bbar & cbar & dbar)}
+ O1_O = {~(A & bbar & cbar & dbar)}
+ O2_O = {~(abar & B & cbar & dbar)}
+ O3_O = {~(A & B & cbar & dbar)}
+ O4_O = {~(abar & bbar & C & dbar)}
+ O5_O = {~(A & bbar & C & dbar)}
+ O6_O = {~(abar & B & C & dbar)}
+ O7_O = {~(A & B & C & dbar)}
+ O8_O = {~(abar & bbar & cbar & D)}
+ O9_O = {~(A & bbar & cbar & D)}
U2DLY PINDLY(10,0,0) DPWR DGND
+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+ O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ PINDLY:
+ O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 = {
+ CASE(
+ DELAY(-1,-1,50ns))}
.ENDS 74145
*
* U1 STIM(4,4) $G_DPWR $G_DGND D C B A
* + IO_STD IO_LEVEL=0
* + 0NS 0 LABEL=START 100NS INCR BY 1 200NS GOTO START -1 TIMES 1800NS 0
X14 A B C D O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 74145
a1 [d c b a] input_vec1
.model input_vec1 d_source(input_file = "decoder.stim")
.TRAN 4e-008 2U 0
.save all
.control
listing
run
eprint d c b a
eprint o0 o1 o2 o3 o4 o5 o6 o7 o8 o9
* save data to input directory
cd $inputdir
eprvcd a b c d o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 > decoder.vcd
* plotting the vcd file with GTKWave
if $oscompiled = 1 | $oscompiled = 8 ; MS Windows
shell start gtkwave decoder.vcd --script nggtk.tcl
else
if $oscompiled = 7 ; macOS, manual tweaking required (mark, insert, Zoom Fit)
shell open -a gtkwave decoder.vcd
else ; Linux and others
shell gtkwave decoder.vcd --script nggtk.tcl &
end
end
quit
.endc
.END

21
examples/p-to-n-examples/decoder.stim Normal file
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@ -0,0 +1,21 @@
* T d c b a
* i
* m
* e
0ns 0s 0s 0s 0s
100ns 0s 0s 0s 1s
200ns 0s 0s 1s 0s
300ns 0s 0s 1s 1s
400ns 0s 1s 0s 0s
500ns 0s 1s 0s 1s
600ns 0s 1s 1s 0s
700ns 0s 1s 1s 1s
800ns 1s 0s 0s 0s
900ns 1s 0s 0s 1s
1.0us 1s 0s 1s 0s
1.1us 1s 0s 1s 1s
1.2us 1s 1s 0s 0s
1.3us 1s 1s 0s 1s
1.4us 1s 1s 1s 0s
1.5us 1s 1s 1s 1s
1.6us 0s 0s 0s 0s

27
src/frontend/logicexp.c
View File

@ -628,39 +628,48 @@ static void gen_models(void)
DS_CREATE(model, 64);
ds_clear(&model);
ds_cat_printf(&model, ".model d_inv_zero_delay d_inverter");
ds_cat_printf(&model,
".model d_inv_zero_delay d_inverter(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__inverter__1 d_inverter");
ds_cat_printf(&model,
".model d__inverter__1 d_inverter(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__buffer__1 d_buffer");
ds_cat_printf(&model,
".model d__buffer__1 d_buffer(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__nand__1 d_nand");
ds_cat_printf(&model,
".model d__nand__1 d_nand(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__and__1 d_and");
ds_cat_printf(&model,
".model d__and__1 d_and(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__xnor__1 d_xnor");
ds_cat_printf(&model,
".model d__xnor__1 d_xnor(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__xor__1 d_xor");
ds_cat_printf(&model,
".model d__xor__1 d_xor(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__nor__1 d_nor");
ds_cat_printf(&model,
".model d__nor__1 d_nor(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_clear(&model);
ds_cat_printf(&model, ".model d__or__1 d_or");
ds_cat_printf(&model,
".model d__or__1 d_or(rise_delay=1.0e-11 fall_delay=1.0e-11)");
u_add_instance(ds_get_buf(&model));
ds_free(&model);

22
src/frontend/udevices.c
View File

@ -719,7 +719,8 @@ struct card *replacement_udevice_cards(void)
return NULL;
}
if (add_zero_delay_inverter_model) {
x = create_xlate_translated(".model d_zero_inv99 d_inverter");
x = create_xlate_translated(
".model d_zero_inv99 d_inverter(rise_delay=1.0e-11 fall_delay=1.0e-11)");
translated_p = add_xlator(translated_p, x);
}
if (add_drive_hilo) {
@ -727,7 +728,8 @@ struct card *replacement_udevice_cards(void)
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated("a1 0 drive___0 dbuf1");
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated(".model dbuf1 d_buffer");
x = create_xlate_translated(
".model dbuf1 d_buffer(rise_delay=1.0e-11 fall_delay=1.0e-11)");
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated(".ends hilo_dollar___lo");
translated_p = add_xlator(translated_p, x);
@ -735,7 +737,8 @@ struct card *replacement_udevice_cards(void)
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated("a2 0 drive___1 dinv1");
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated(".model dinv1 d_inverter");
x = create_xlate_translated(
".model dinv1 d_inverter(rise_delay=1.0e-11 fall_delay=1.0e-11)");
translated_p = add_xlator(translated_p, x);
x = create_xlate_translated(".ends hilo_dollar___hi");
translated_p = add_xlator(translated_p, x);
@ -2499,6 +2502,11 @@ static char *get_estimate(struct timing_data *tdp)
These functions are called from u_process_model(), and the delay strings
are added to the timing model Xlator by add_delays_to_model_xlator().
*/
static char *get_zero_rise_fall(void)
{
return tprintf("(rise_delay=1.0e-11 fall_delay=1.0e-11)");
}
static char *get_delays_ugate(char *rem)
{
char *rising, *falling, *delays = NULL;
@ -2514,7 +2522,11 @@ static char *get_delays_ugate(char *rem)
if (strlen(rising) > 0 && strlen(falling) > 0) {
delays = tprintf("(rise_delay = %s fall_delay = %s)",
rising, falling);
} else {
delays = get_zero_rise_fall();
}
} else {
delays = get_zero_rise_fall();
}
delete_timing_data(tdp1);
delete_timing_data(tdp2);
@ -2536,7 +2548,11 @@ static char *get_delays_utgate(char *rem)
if (rising && falling) {
if (strlen(rising) > 0 && strlen(falling) > 0) {
delays = tprintf("(delay = %s)", rising);
} else {
delays = tprintf("(delay=1.0e-11)");
}
} else {
delays = tprintf("(delay=1.0e-11)");
}
delete_timing_data(tdp1);
delete_timing_data(tdp2);

4
visualc/vngspice.vcxproj
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@ -1005,6 +1005,7 @@
<ClInclude Include="..\src\include\ngspice\ipctiein.h" />
<ClInclude Include="..\src\include\ngspice\jobdefs.h" />
<ClInclude Include="..\src\include\ngspice\lsort.h" />
<ClInclude Include="..\src\include\ngspice\logicexp.h" />
<ClInclude Include="..\src\include\ngspice\macros.h" />
<ClInclude Include="..\src\include\ngspice\material.h" />
<ClInclude Include="..\src\include\ngspice\matldefs.h" />
@ -1500,6 +1501,7 @@
<ClCompile Include="..\src\frontend\interp.c" />
<ClCompile Include="..\src\frontend\inventory.c" />
<ClCompile Include="..\src\frontend\linear.c" />
<ClCompile Include="..\src\frontend\logicexp.c" />
<ClCompile Include="..\src\frontend\measure.c" />
<ClCompile Include="..\src\frontend\misccoms.c" />
<ClCompile Include="..\src\frontend\miscvars.c" />
@ -2755,4 +2757,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>
</Project>