rlar
|
2bcadae16c
|
missing newline at end of file
|
2012-10-20 19:49:10 +02:00 |
h_vogt
|
3ca1235602
|
gnuplot.c: improve scaling of y axis
|
2012-10-09 19:47:24 +02:00 |
|
h_vogt
|
177964b4a6
|
XSPICE example: delta-sigma converter
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2012-08-14 23:06:34 +02:00 |
|
h_vogt
|
f1d0d40753
|
demonstrate effect of W crossing binning limits
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2012-08-07 23:11:52 +02:00 |
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h_vogt
|
5d0c3182d3
|
add BSIM3 model parameters for loop filer with transistor charge pump
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2012-08-05 20:15:53 +02:00 |
|
h_vogt
|
e1df8eb739
|
example, add 'alter @m1[w]=11u' using binning and model change
|
2012-08-05 20:06:06 +02:00 |
dwarning
|
96dd397251
|
correct the plot output
|
2012-08-05 12:06:11 +02:00 |
|
h_vogt
|
19a67fb7c5
|
pll: just include one of the two vco available
(avoid a bug which has been removed only recently)
|
2012-08-04 00:22:25 +02:00 |
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h_vogt
|
a0db6f0ccd
|
update to XSPICE phase-locked loop example
|
2012-08-03 23:22:54 +02:00 |
|
h_vogt
|
6cd13e0475
|
pll-xspice-fstep.cir: pll with ref frequency steps
|
2012-07-31 18:05:10 +02:00 |
|
h_vogt
|
c31fc334f6
|
pll-xspice.cir: save command added
|
2012-07-31 17:31:28 +02:00 |
|
h_vogt
|
c0b5a78097
|
new XSPICE example: use trtol=1
less ripple, but longer simulation time
|
2012-07-30 00:01:56 +02:00 |
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h_vogt
|
85ece25a3a
|
new XSPICE example: mixed mode pll circuit
|
2012-07-29 13:52:23 +02:00 |
|
h_vogt
|
d072ab80d1
|
memristor example, parameters changed
|
2012-06-13 19:15:26 +02:00 |
|
h_vogt
|
fde8c46356
|
add ac and dc simulation to memristor model
|
2012-06-13 19:15:25 +02:00 |
|
h_vogt
|
f53eb5cf78
|
memristor code model in extradev
|
2012-06-13 19:15:24 +02:00 |
|
h_vogt
|
1cbc41cc32
|
memristor subcircuit model example
|
2012-06-13 19:15:19 +02:00 |
|
rlar
|
3d34b22ebf
|
fix file modes
|
2012-06-12 21:26:29 +02:00 |
|
h_vogt
|
890d049a5b
|
uic to end of line in pss
|
2011-08-09 19:58:40 +00:00 |
pnenzi
|
af16208f9c
|
Moved pss example files from tests directory to examples directory
|
2011-08-07 18:51:05 +00:00 |
|
h_vogt
|
926a7b338c
|
'filesource' test
|
2011-06-23 19:56:46 +00:00 |
|
h_vogt
|
747c606e30
|
remove bug in command meas, allow / and \ in Windows file paths
|
2011-06-18 17:45:43 +00:00 |
|
dwarning
|
c7763a6e83
|
to much puts
|
2011-03-10 20:12:07 +00:00 |
|
rlar
|
7880d5bd8e
|
cleanup some whitespace errors and prototypes
|
2011-02-19 16:47:30 +00:00 |
|
h_vogt
|
c162d3273f
|
vsrc trrandom option
|
2011-01-16 19:19:42 +00:00 |
|
dwarning
|
6aba89bbed
|
convergence with higher epi resistances
|
2011-01-15 22:22:59 +00:00 |
|
h_vogt
|
97605a5df7
|
models 1N4001 also in subcircuits
|
2011-01-06 19:15:20 +00:00 |
|
h_vogt
|
1ea76af678
|
add statistical functions to numparam and nutmeg parsers
|
2010-12-28 19:01:30 +00:00 |
|
h_vogt
|
4d1202d7ef
|
rts example
|
2010-12-18 17:16:00 +00:00 |
|
h_vogt
|
3a479ade38
|
meas added
|
2010-11-28 10:47:35 +00:00 |
|
h_vogt
|
3070001ed1
|
transient noise example added
|
2010-11-28 09:59:40 +00:00 |
|
h_vogt
|
19babde1e1
|
change to version 3.3.0 allowing multithreading
|
2010-11-27 17:11:36 +00:00 |
|
h_vogt
|
ffc3032df7
|
bsim3 parameter sets
|
2010-11-27 17:01:54 +00:00 |
|
h_vogt
|
5e1ed023c6
|
transient noise simulation
|
2010-11-27 16:36:03 +00:00 |
|
h_vogt
|
c140c3d532
|
improved comments
|
2010-10-16 13:29:07 +00:00 |
|
h_vogt
|
afdf6ee134
|
new command wrs2p
|
2010-10-16 12:05:09 +00:00 |
|
h_vogt
|
7fd724c060
|
new Monte Carlo example folder
|
2010-09-25 14:57:24 +00:00 |
|
h_vogt
|
ed625c5509
|
update
|
2010-09-15 22:00:04 +00:00 |
|
rlar
|
b1f6da536a
|
whitespace cleanup, add missing trailing newlines
|
2010-09-07 19:04:20 +00:00 |
|
dwarning
|
a4d4e91ab4
|
no message
|
2010-08-29 09:24:38 +00:00 |
|
h_vogt
|
adc911d412
|
xspice examples
|
2010-05-14 20:33:20 +00:00 |
|
dwarning
|
49aadcca58
|
new operation in control blocks
|
2010-04-11 09:04:55 +00:00 |
|
dwarning
|
f59646cef8
|
txl model needs g value
|
2010-03-03 20:03:34 +00:00 |
|
dwarning
|
ba54c4d9b8
|
big kspice model update
|
2010-02-07 18:16:17 +00:00 |
|
dwarning
|
0bea3e294a
|
fix the c matrix unsymmetry
|
2010-01-28 20:17:38 +00:00 |
|
dwarning
|
64e383961b
|
matrixes must be complete to prevent access violation
|
2010-01-24 14:17:00 +00:00 |
|
dwarning
|
609e109029
|
matrixes must be complete to prevent access violation
|
2010-01-23 22:20:08 +00:00 |
|
dwarning
|
a34c4a3e53
|
matrixes must be complete to prevent access violation
|
2010-01-23 22:12:53 +00:00 |
|
dwarning
|
531ffc1403
|
Hopefully more meaningful transmissionline examples
|
2010-01-17 17:11:42 +00:00 |
|
h_vogt
|
28d5114f43
|
comments, new examples
|
2009-12-28 08:34:55 +00:00 |