XSPICE example: delta-sigma converter
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A simple delta sigma converter using XSPICE
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according to
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Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
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Fig. 2.13, p. 31; Fig. 2.27, p.58
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delta-sigma-1.cir
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converter complete, tested against sine input
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mod1-ct.cir
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first order modulator
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consists of analog continuous time integrator and
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digitally latched comparator
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count-latch-dac.cir
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contains subcircuits of
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10 bit digital latch
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10 bit counter, non-revolving, saturating
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simple 10 bit DAC with analog B source
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mod1-ct-test.cir
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test of modulator with sine input, shows noise shaping 20dB/decade
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counter-test.cir
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simple test with reset
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* counter, latch DAC
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* 10 bit synchronous digital counter
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* inhibit at overflow, no revolving
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.subckt count10 din dinb dclk drs dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
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* j k clk set reset out nout
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ajk1 din dinb diclk ds1 drs dout1 dnout1 jkflop
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ajk2 dout1 dout1 diclk ds2 drs dout2 dnout2 jkflop
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ajk3 djk3 djk3 diclk ds3 drs dout3 dnout3 jkflop
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ajk4 djk4 djk4 diclk ds4 drs dout4 dnout4 jkflop
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ajk5 djk5 djk5 diclk ds1 drs dout5 dnout5 jkflop
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ajk6 djk6 djk6 diclk ds2 drs dout6 dnout6 jkflop
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ajk7 djk7 djk7 diclk ds3 drs dout7 dnout8 jkflop
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ajk8 djk8 djk8 diclk ds4 drs dout8 dnout8 jkflop
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ajk9 djk9 djk9 diclk ds3 drs dout9 dnout9 jkflop
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ajk10 djk10 djk10 diclk ds4 drs dout10 dnout10 jkflop
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aand1 [dout1 dout2] djk3 and1
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aand2 [dout1 dout2 dout3] djk4 and1
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aand3 [dout1 dout2 dout3 dout4] djk5 and1
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aand4 [dout1 dout2 dout3 dout4 dout5] djk6 and1
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aand5 [dout1 dout2 dout3 dout4 dout5 dout6] djk7 and1
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aand6 [dout1 dout2 dout3 dout4 dout5 dout6 dout7] djk8 and1
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aand7 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8] djk9 and1
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aand8 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9] djk10 and1
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* inhibit revolving of counter, just let it saturate
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* (footnote p. 57)
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aand_all [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10] dinhibit nand1
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aandclk [dclk dinhibit] diclk and1
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.model nand1 d_nand(rise_delay = 1e-9 fall_delay = 1e-9
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+ input_load = 0.5e-12)
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.model and1 d_and(rise_delay = 1e-9 fall_delay = 1e-9
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+ input_load = 0.5e-12)
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.model jkflop d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9
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+ reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9
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+ fall_delay = 1e-9)
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.ends count 10
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** 10 bit edge triggered latch
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.subckt latch10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10
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+ dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dclk
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*data clk set reset out nout
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aff1 din1 dclk dzero dzero dout1 dnout1 flop1
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aff2 din2 dclk dzero dzero dout2 dnout2 flop1
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aff3 din3 dclk dzero dzero dout3 dnout3 flop1
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aff4 din4 dclk dzero dzero dout4 dnout4 flop1
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aff5 din5 dclk dzero dzero dout5 dnout5 flop1
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aff6 din6 dclk dzero dzero dout6 dnout6 flop1
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aff7 din7 dclk dzero dzero dout7 dnout7 flop1
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aff8 din8 dclk dzero dzero dout8 dnout8 flop1
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aff9 din9 dclk dzero dzero dout9 dnout9 flop1
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aff10 din10 dclk dzero dzero dout10 dnout10 flop1
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.model flop1 d_dff(clk_delay = 1e-9 set_delay = 0
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+ reset_delay = 0 ic = 0 rise_delay = 1e-9
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+ fall_delay = 1e-9)
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.ends latch10
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** emulation of 10 bit DAC
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.subckt dac10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 aout
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.param vref=1
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abridge1 [din1 din2 din3 din4 din5 din6 din7 din8 din9 din10]
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+ [ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10] dac1
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BVout aout 0 V = 'vref'*(v(ain10)/2 + v(ain9)/4 + v(ain8)/8 + v(ain7)/16 + v(ain6)/32 +
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+ v(ain5)/64 + v(ain4)/128 + v(ain3)/256 + v(ain2)/512 + v(ain1)/1024)
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.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
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+ input_load = 5.0e-12 t_rise = 1e-9
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+ t_fall = 1e-9)
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.ends dac10
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* 10 bit synchronous digital counter
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* inhibit at overflow, no revolving
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* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
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* Fig. 2.27, p. 58
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* clock generation
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* PULSE(V1 V2 TD TR TF PW PER)
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vclk aclk 0 dc 0 pulse(0 1 1u 2n 2n 1u 2u)
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* reset generation
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* single pulse, actual value stored in latch and read by DAC
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vres ars 0 dc 0 pulse(0 1 1.1m 2n 2n 1u 2.2m)
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vone aone 0 dc 1
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vzero azero 0 dc 0
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* digital one
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* digital zero
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abridge1 [aone azero] [done dzero] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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* digital clock
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* digital reset
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abridge2 [aclk ars] [dclk dreset] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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XCounter done done dclk dreset dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
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Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
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+ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 dreset
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+ latch10
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Xdac dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adacout dac10
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.include count-latch-dac.cir
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.control
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tran 1u 2.5m
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eprint dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 > digi4b.txt
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eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 >> digi4b.txt
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plot adacout
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.endc
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.end
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* delta sigma A/D converter 9 bit
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* first-order continuous time delta sigma modulator
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* sinc filter with counter
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* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
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* Fig. 2.13, p. 31; Fig. 2.27, p.58
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** sine input signal parameters
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.param infreq=500 inampl=0.5
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** clock
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.param clkfreq=5Meg
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** simulation time
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.param simtime = 2m
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.csparam simtime = 'simtime'
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** sample clock cycles
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.param samples=500
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.global dzero done
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** input signal
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* SIN(VO VA FREQ TD THETA)
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vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0)
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* steps from -0.5 to 0.4
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*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3
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*+ 0.601m -0.2 0.8m -0.2 0.801m -0.1 1.0m -0.1 1.001m 0.0 1.2m 0.0 1.201m 0.1 1.4m 0.1
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*+ 1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4)
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** clock and constant logic levels
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* PULSE(V1 V2 TD TR TF PW PER)
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vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
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* digital one
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* digital zero
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vone aone 0 dc 1
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vzero azero 0 dc 0
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abridge1 [aone azero] [done dzero] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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* digital clock
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abridge2 [aclk] [dclk] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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****** delta-sigma converter****************************************************************
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* modulator
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* inp inm: analog in + -
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* dclk digital clock in
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* dv, dvb: modulator non-inverting/inverting out
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Xmod inp inm dclk dv dvb mod1
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* sinc filter, decimator
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* dlout1 ..dlout10: converter 10 bit digital out
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xsinc dv dvb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1
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********************************************************************************************
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** DACs for measuring and plotting
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* converter output
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Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10
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* counter inside of sinc filter
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Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
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+ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10
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* load modulator mod1 subcircuit
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.include mod1-ct.cir
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* load counter, d-latch and 10 bit DAC
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.include count-latch-dac.cir
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** sinc filter 1st order subcircuit
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.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10
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XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
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Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
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+ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1
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+ latch10
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* digital divider dclk/samples
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adivn dclk ddivn divider
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.model divider d_fdiv(div_factor = 'samples' high_cycles = 1
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+ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9)
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* clock delays
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adelay ddivn ddivndel1 buff1 ; set latch
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adelay2 ddivndel1 ddivndel2 buff1 ; reset counter
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.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8'
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+ input_load = 0.5e-12)
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.ends sinc1
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** for plotting
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abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1
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.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
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+ input_load = 5.0e-12 t_rise = 1e-9
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+ t_fall = 1e-9)
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.control
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save inp inm adaclout adaccout ; save memory space
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tran 0.1u $&simtime
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* analog out, scaled 'manually'; sinc filter counter; analog differential in
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plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6
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* modulator dig out
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* eprint dv > digi1.txt
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*
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*eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10
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*+ xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
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*+ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 > digi4b.txt
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.endc
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.end
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@ -0,0 +1,52 @@
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* first-order delta sigma modulator
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* continuous time
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* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
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* Fig. 2.13, p. 31
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** signal
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.param infreq=13k inampl=0.3
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** clock
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.param clkfreq=5Meg
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** simulation time
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.param simtime = 5m
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.csparam simtime = 'simtime'
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** input signal
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*SIN(VO VA FREQ TD THETA)
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vin in+ in- dc 0 sin(0 'inampl' 'infreq' 0 0)
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* clock generation
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* PULSE(V1 V2 TD TR TF PW PER)
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vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
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* digital one
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* digital zero
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vone aone 0 dc 1
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vzero azero 0 dc 0
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abridge1 [aone azero] [done dzero] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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* digital clock
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abridge2 [aclk] [dclk] adc_buff
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.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
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Xmod in+ in- dclk dv dvb mod1
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* load mod1 subcircuit
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.include mod1-ct.cir
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.control
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save xmod.adffq in+ in- xmod.outintp xmod.outintn
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tran 0.01u $&simtime
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* digit density vs input
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plot xmod.adffq "v(in+) - v(in-)" xlimit 0.1m 0.2m
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* modulator integrator out, digital out
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plot xmod.outintp-xmod.outintn xmod.adffq xlimit 0.140m 0.148m
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*eprint dv dclk > digi1.txt
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linearize xmod.adffq
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fft xmod.adffq
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* noise shaping 20dB/decade
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plot db(xmod.adffq) xlimit 10k 1Meg xlog ylimit -20 -120
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.endc
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.end
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* delta sigma modulator
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* first order, continuous time
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.subckt mod1 ainp ainn dclk ddffq ddffqb
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* integrator and summer
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Ri1 ainn inintn 500
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Rf1 adffq inintn 500
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Cint1 outintp inintn 1n
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.IC v(outintp) = 0 v(inintp) = 0
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*
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Rshunt1 outintp 0 100Meg
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Rshunt2 initn 0 100Meg
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*
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Ri2 ainp inintp 500
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Rf2 adffqb inintp 500
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Cint2 outintn inintp 1n
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.IC v(outintn) = 0 v(inintn) = 0
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*
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Rshunt3 outintn 0 100Meg
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Rshunt4 inintp 0 100Meg
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*
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aint %vd(inintp inintn) %vd(outintp outintn) amp
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.model amp gain ( in_offset =0.0 gain =100000
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+ out_offset = 0)
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* latched comparator (code model or B source, analog in, digital out)
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*acomp %vd(outintp outintn) acompout limit5
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*.model limit5 limit(in_offset=0 gain=100000 out_lower_limit=-1.0
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*+ out_upper_limit=1.0 limit_range=0.10 fraction=FALSE)
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*
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BComp acompout 0 V = (V(outintp) - V(outintn)) >= 0 ? 1 : -1
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*
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abridge2 [acompout] [dcompout] adc_buff
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.model adc_buff adc_bridge(in_low = 0 in_high = 0)
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*
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* D flip flop: data clk set reset out nout
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adff1 dcompout dclk ds drs ddffq ddffqb flop2
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.model flop2 d_dff(clk_delay = 1e-9 set_delay = 1.0e-9
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+ reset_delay = 1.0e-9 ic = 0 rise_delay = 1.0e-9
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+ fall_delay = 1e-9)
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abridge1 [ddffq ddffqb dclk] [adffq adffqb aclk] dac1
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.model dac1 dac_bridge(out_low = -1 out_high = 1 out_undef = 0
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+ input_load = 5.0e-12
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.ends mod1
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