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74 Commits

Author SHA1 Message Date
Brian Taylor cc101495a5 Fix the xspice transmission_line examples. 
Also, cherry pick:
commit 87d09def9c (origin/bt_dev)
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Sun May 18 14:01:47 2025 -0700

    Fix memory leak in xspice oneshot.
 2025-07-29 10:57:55 +02:00
Vadim Kuznetsov 70ee0f8ef5 Add examples 2025-07-29 10:54:37 +02:00
Holger Vogt d2ded9fa2c Tiny modifications of SEE examples 2025-07-29 10:47:32 +02:00
Holger Vogt 3fb1ea1c39 Unix line endings 
rusage added
 2025-07-29 10:46:39 +02:00
Holger Vogt 9d7db2166a New example for seegen: CMOS comparator 2025-07-29 10:46:18 +02:00
Holger Vogt 07f8c3558b Add a monitoring output the the seegen instance 2025-07-29 10:45:30 +02:00
Holger Vogt b628032d7d Add a generator for SEE (single event effects) pulses as a code model. 
To be used like
aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d')
see README.SEEgenerator for details
 2025-07-29 10:39:58 +02:00
Giles Atkinson bba4046d55 Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir, 
behaviour as before.  Add similar pll-digital-iplot.cir as a
demonstration of iplot with analogue and digital nodes.
 2025-05-24 11:28:42 +02:00
Giles Atkinson 592b99d0ef Rename pll-xspice.cir to shared-pll-xspice.cir to prepare for split. 2025-05-24 11:28:34 +02:00
Giles Atkinson c7c85ecadc Add co-simulation with VHDL, using the GHDL compiler and d_cosim. 2025-05-24 11:05:33 +02:00
Brian Taylor 00ad25fbc9 Fix d_process named pipes example. Use the correct gtkwave command for MacOS. 
The following is also required:
commit 527b8378e8
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Wed Apr 10 13:24:48 2024 -0700

    Fix circuits so that gtkwave tests run on MacOS. Add encoder/decoder example.
 2025-05-24 11:03:52 +02:00
Giles Atkinson fd3827af40 Fix ordering of parameter definition and use. 
Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
 2025-05-24 11:00:18 +02:00
Holger Vogt fdbb62844c Example for sending a text string over the subcircuit boundary. 2024-12-06 22:48:31 +01:00
Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog 
source and large parts of the example circuits between Verilator and
Icarus Verilog.  Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
 2024-11-02 22:30:32 +01:00
Giles Atkinson c18447f9f5 Add the support files for co-simulation with Verilog code 
compiled by Verilator.  Also add script files to Visual Studio builds
that are already installed by the Makefile builds.
 2023-11-27 20:55:59 +00:00
Giles Atkinson f6f7319792 Add null-pointer checks to some code that crashed when trying 
to .print results from a non-existent analysis.  Also remove the
troublesome .plot and .print lines from two examples.
 2023-11-09 12:07:31 +00:00
Brian Taylor 864ef7925c Add notes on the structure and organization of an external d_process program. 2023-10-28 19:43:50 +02:00
Brian Taylor 5c6b9f03b5 Fix the zero count. 2023-10-28 19:43:41 +02:00
Brian Taylor 1f5f7ae439 Update d_process examples. 2023-10-28 19:43:36 +02:00
Brian Taylor 09f070f582 Error handling improvements in cfunc.mod. Ensure that d_process.h wiil always respond to version and interface checks sent from sendheader. This is needed so that the pipe reads in sendheader do not cause Windows to hang when the interface version and in/out counts do not match. This hang was the cause of errors not being reported and the Windows gui hanging. Startup and header checks are now detected in cm_d_process, and the simulator will run but with runtime errors since a d_process model cannot be completely instantiated after initial errors. It would be good to find a means of gracefully halting the simulation run. 2023-10-28 11:00:33 +02:00
Brian Taylor 4530cde8e2 Use Xspice cm_message_send to report errors rathen than printing to stderr and calling exit. When a d_process model has errors found in start(), sendheader(), and dprocess_exchangedata() these are reported, but if the model is run a SIGINT is raised. There must be a better way of stopping the simulator. 2023-10-28 11:00:18 +02:00
Brian Taylor 182764a894 Add examples/xspice/d_process. 2023-10-28 11:00:12 +02:00
Giles Atkinson 5114d6c2f4 Add an option to the iplot command: -d sets the number of simulation 
steps before the window is shown.  The value can be chosen to
limit rapid resizing when starting and that is used in the PLL examples.
 2023-07-15 11:29:32 +02:00
Holger Vogt a48cc44c7f Example input file for 'iplot -w' option 2023-05-27 10:46:55 +02:00
Holger Vogt af9f25e985 Various filter examples using Laplace expression x_fer 2023-01-20 15:07:37 +01:00
Holger Vogt 925dc55a73 rename example file 2022-12-11 15:28:23 +01:00
Holger Vogt ca1974ff37 Examples moved to folder /various 2022-12-11 15:28:01 +01:00
Holger Vogt 751019b447 Examples for d_pwm and d_osc 2022-12-11 15:27:42 +01:00
Holger Vogt ec6a902fb9 Fix a bug in simple diode, when ilimit is set, but not epsilon. 
Make model more similar to LTSPICE
Add an example
 2022-10-08 16:50:38 +02:00
Holger Vogt cb42895dad example for pwlts source code model 2022-10-07 13:39:33 +02:00
Holger Vogt c8ed9590b7 Handle the case when control voltages on and off are equal. 
Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
 2022-10-07 13:12:56 +02:00
Holger Vogt 2deefe1fbc New tables for MOS devices 2022-10-07 13:11:18 +02:00
Holger Vogt 765d2e8a0e Return data to input directory. 2022-10-07 13:10:51 +02:00
Holger Vogt a69dd1bcde Simplify the NMOS or PMOS selection by setting only one parameter 
'mostype'
ngspice-37+ is required.
 2022-10-07 13:10:06 +02:00
Holger Vogt afde37c35d add y-axis label 2022-02-01 12:21:08 +01:00
Holger Vogt 2981d0f56d Use 'esave none' to reduce memory consumption. 
Only analg nodes are to be saved.
 2022-01-09 10:58:51 +01:00
Holger Vogt 738ac4863c Obtain memory and simulation time 
Add rusage information command
 2022-01-03 22:11:15 +01:00
Holger Vogt 70e4d2157e New names for the (experimental) ramp-time capacitor and inductor code models 2021-10-29 16:28:57 +02:00
Holger Vogt 05624bedd3 move examples file to prpoer xspice folder 2021-08-03 15:53:11 +02:00
Holger Vogt 6c3b14e396 make simulation faster, allow batch mode 2020-03-15 08:50:57 +01:00
Holger Vogt 9dec5f5f1e An example for non-convergence of the pll if the stepszelimit is removed. 
Adding a somewhat relaxed limit by TMAX in the tran command will speed
up the simulation by a factor of 1.5 without compromising the result.
 2019-03-21 20:26:24 +01:00
Holger Vogt f46135cc03 script to start GTKWave 2018-10-13 22:47:53 +02:00
dwarning bd5379d760 one tran analysis is sufficient 2018-09-14 20:34:27 +02:00
Holger Vogt 3138811acd README for the table model and its table directory 2018-09-02 18:05:10 +02:00
Holger Vogt 925cb49ff2 Add some description, correct minor bugs. 2018-09-02 18:05:06 +02:00
Holger Vogt 800c9711f2 add a flag 'type of the union' to safely free model->param[i]->element, 
if it contain a malloced string
 2018-08-28 21:29:05 +02:00
Holger Vogt f988dfad93 add plotting to the example 2018-08-27 12:20:30 +02:00
Holger Vogt 9becf1313a complex model: a script loads two circuits with MOS and 
bipolar table models, and run a sequence of dc simulations
with switching the circuit.
 2018-08-18 11:28:13 +02:00
Holger Vogt bb86b137a7 add 'reset' to fix a huge memory leak 2018-08-18 11:27:38 +02:00
Holger Vogt e99985a156 add two commands 'reset' to avoid huge memory leak 2018-08-18 11:27:08 +02:00