Add some description, correct minor bugs.
This commit is contained in:
Holger Vogt
parent
12c864fb5a
commit
925cb49ff2
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@ -12,7 +12,7 @@
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** Lmin=0.02 Lmax=10 Wmin=0.6 Wmax=20
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** By Mohan Dunga, Wenwei Yang 05/18/2007
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.MODEL N1 NMOS LEVEL = 14
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.MODEL NBSIM4 NMOS LEVEL = 14
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+VERSION = 4.7 BINUNIT = 1 PARAMCHK= 0 MOBMOD = 0
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+CAPMOD = 1 IGCMOD = 1 IGBMOD = 1 GEOMOD = 1
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@ -12,7 +12,7 @@
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** Lmin=0.02 Lmax=10 Wmin=0.6 Wmax=20
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** By Mohan Dunga, Wenwei Yang 05/18/2007
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.MODEL P1 PMOS LEVEL = 14
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.MODEL PBSIM4 PMOS LEVEL = 14
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+VERSION = 4.6.5 BINUNIT = 1 PARAMCHK= 0 MOBMOD = 0
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+CAPMOD = 2 IGCMOD = 1 IGBMOD = 1 GEOMOD = 1
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@ -1,4 +1,17 @@
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** NMOSFET: table generator with BSIM4 2D (Vdrain, Vgate)
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* This file may be run by 'ngspice table-generator-b4-2d.sp'
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* It will generate a 2D data table by simulating the MOS drain current
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* as function of drain and gate voltages. The simulation uses
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* the ngspice BSIM4.6.1 MOS model and Berkeley model parameters.
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* This table is an input file for the XSPICE 2D table model.
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* You have to select NMOS or PMOS by manually editing this file: currently
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* PMOS is selected. For NMOS change '*' in column 1
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* for CSPARAM, m1, outfile, echo *table...
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* In addition you may change the step sizes vdstep vgstep vbstep in CSPARAM
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* to obtain the required resolution for the data.
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* These tables will contain pure dc data. For transient simulation you may
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* need to add some capacitors to the device model for a 'real world' simulation.
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*NMOS
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*.csparam vdstart=-0.1
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*.csparam vdstop=1.8
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@ -16,19 +29,20 @@
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.csparam vgstep=0.01
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** Circuit Description **
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*m1 2 1 3 0 n1 L=0.13u W=10.0u rgeoMod=1
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m1 2 1 3 0 p1 L=0.13u W=10.0u rgeoMod=1
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*m1 2 1 3 0 nbsim4 L=0.13u W=10.0u rgeoMod=1
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m1 2 1 3 0 pbsim4 L=0.13u W=10.0u rgeoMod=1
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vgs 1 0 1.8
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vds 2 0 1.8
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vss 3 0 0
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.control
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** output file **
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set outfile = "bsim4n-2d-1.table"
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*set outfile = "bsim4n-2d-1.table"
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set outfile = "bsim4p-2d-1.table"
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*dc vds 0 1.8 0.05 vgs 0 1.8 0.3
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save i(vss)
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echo *table for nmos bsim 4 > $outfile
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*echo *table for nmos bsim 4 > $outfile
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echo *table for pmos bsim 4 > $outfile
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let xcount = floor((vdstop-vdstart)/vdstep) + 1
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let ycount = floor((vgstop-vgstart)/vgstep) + 1
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@ -81,7 +95,7 @@ end
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.endc
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.include ./modelcards/modelcard.pmos
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.include ./modelcards/modelcard.nmos
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.end
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@ -1,4 +1,17 @@
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** NMOSFET: table generator with BSIM4 2D (Vdrain, Vgate)
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** NMOSFET: table generator with BSIM4 3D (Vdrain, Vgate, Vbulk)
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* This file may be run by 'ngspice table-generator-b4-3d.sp'
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* It will generate a 3D data table by simulating the MOS drain current
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* as function of drain and gate voltages. The simulation uses
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* the ngspice BSIM4.6.1 MOS model and Berkeley model parameters.
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* This table is an input file for the XSPICE 3D table model.
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* You have to select NMOS or PMOS by manually editing this file: currently
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* NMOS is selected. For PMOS change '*' in column 1
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* for CSPARAM, m1, outfile, echo *table...
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* In addition you may change the step sizes vdstep vgstep vbstep in CSPARAM
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* to obtain the required resolution for the data.
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* These tables will contain pure dc data. For transient simulation you may
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* need to add some capacitors to the device model for a 'real world' simulation.
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*NMOS
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.csparam vdstart=-0.1
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.csparam vdstop=1.8
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@ -22,8 +35,8 @@
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*.csparam vbstep=0.2
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** Circuit Description **
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m1 2 1 3 4 n1 L=0.13u W=10.0u rgeoMod=1
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*m1 2 1 3 4 p1 L=0.13u W=10.0u rgeoMod=1
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m1 2 1 3 4 nbsim4 L=0.13u W=10.0u rgeoMod=1
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*m1 2 1 3 4 pbsim4 L=0.13u W=10.0u rgeoMod=1
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vgs 1 0 1.8
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vds 2 0 1.8
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vss 3 0 0
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@ -32,9 +45,11 @@ vbs 4 0 0
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.control
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** output file **
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set outfile = "bsim4n-3d-1.table"
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*set outfile = "bsim4p-3d-1.table"
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save i(vss)
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echo * 3D table for nmos bsim 4 > $outfile
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*echo * 3D table for nmos bsim 4 > $outfile
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let xcount = floor((vdstop-vdstart)/vdstep) + 1
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let ycount = floor((vgstop-vgstart)/vgstep) + 1
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@ -101,7 +116,7 @@ while lcz < zcount
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end
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.endc
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.include ./modelcards/modelcard.pmos
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.include ./modelcards/modelcard.nmos
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.include ./modelcards/modelcard.pmos
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.end
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@ -1,5 +1,15 @@
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** npn bipolar: table generator with q 2D (Vce, Ib)
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*NMOS
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* This file may be run by 'ngspice table-generator-q-2d.sp'
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* It will generate a 2D data table by simulating the bipolar collector current
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* as function of collector voltage and base current. The simulation uses
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* the ngspice bipolar model and model parameters of a clc409 transitor.
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* This table is an input file for the XSPICE 2D table model.
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* You may change the step sizes vcstep ibstep in CSPARAM
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* to obtain the required resolution for the data.
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* These tables will contain pure dc data. For transient simulation you may
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* need to add some capacitors to the device model for a 'real world' simulation.
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*NPN
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.csparam vcstart=-0.2
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.csparam vcstop=6.4
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.csparam vcstep=0.05
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@ -79,14 +89,11 @@ while lcy < ycount
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let lcy = lcy + 1
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end
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label next
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end
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.endc
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.MODEL QINN NPN
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+ IS =0.166f BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01
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+ IKF=2.462E-02 ISE=2.956E-17 NE =1.197E+00 BR =3.719E+01
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