There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.
Fully compatible with older versions of Apicula.
Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Refactor in order to detect networks that will be routed in a special
mode earlier. This makes it possible to mark the source of such networks
as a global buffer, thereby removing their influence on element
placement.
In addition, timing classes are set for some cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A simple router that takes advantage of the fact that in each cell with
DFFs their CLK inputs can directly connect to the global clock network.
Networks with a large number of such sinks are sought and then each
network is assigned to the available independent global clock networks.
There are limited possibilities for routing mixed networks, that is,
when the sinks are not only CLKs: in this case an attempt is made to use
wires such as SN10/20 and EW10/20, that is, one short transition can be
added between the global clock network and the sink.
* At this time, networks with a source other than the I/O pin are not
supported. This is typical for Tangnano4k and runber boards.
* Router is disabled by default, you need to specify option
--enable-globals to activate
* No new chip bases are required. This may change in the distant future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the Gowin chips, the tiles are connected to each other by a one-hop
wire, among others. There are 4 one-hop wires, of which 2 are shared
between north/south and east/west, have three names: e.g. SN10 and N110
and S110.
But only one of them, the first, occurs as a sink for PIP, that is, you
can not get a route that would pass through the S110 for example.
This commit corrects the names to SN?0 and EW?0 at the wire creation
stage to avoid dead wires.
In addition, the SN?0 and EW?0 are among the few sinks for global clock
wires and now there is the possibility of a more optimal clock routing.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Compatible with older versions of apicula bases.
Also small fixes and as the number of virtual Bels grows it is necessary
to assign them Z coordinate in a centralized way to avoid conflicts and
for this purpose introduced the BelZ enum.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
GSR is added automatically if it was not instantiated by the user explicitly.
Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
The model should be recognized by the partnumber, --family is needed
only if the same partnumbers belong to different models.
This is done in order to automatically generate parameters for calling
nextpnr from Gowin files without problems: there also only partnumber is
used and only in some cases the model is specified with the -name
parameter and GW1NZ-1 is not such a case.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The new primitive appears as an amalgamation of two existing OBUF
primitives. Compatible with older versions of apicula, although, of
course, using TLVDS_OBUF with old databases will not bring the desired
result, but no crash.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the vendor IDE, there's a device family named GW1N-9C (which seems to
mean C revision of GW1N-9), in which the model numbers are all the same
with GW1N-9.
Add an option to nextpnr-gowin to allow manually specified family for
this situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
YRabbit
gatecat
Pepijn de Vos
Tim Pambor
Verneri Hirvonen
Icenowy Zheng