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nextpnr
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hook up CE maybe

This commit is contained in:
Pepijn de Vos 2022-06-16 11:38:23 +02:00
parent de1bee9352
commit b7992ec772
3 changed files with 4 additions and 0 deletions
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2
gowin/arch.cc
View File

@ -1094,6 +1094,8 @@ Arch::Arch(ArchArgs args) : args(args)
addBelInput(belname, id_CLK, id(buf));
snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
addBelInput(belname, id_LSR, id(buf));
snprintf(buf, 32, "R%dC%d_CE%d", row + 1, col + 1, 2);
addBelInput(belname, id_CE, id(buf));
break;
// fall through the ++
case ID_LUT7:

1
gowin/cells.cc
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@ -54,6 +54,7 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
new_cell->addInput(names[i]);
}
new_cell->addInput(id_CLK);
new_cell->addInput(id_CE);
new_cell->addInput(id_LSR);
} else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {

1
gowin/pack.cc
View File

@ -708,6 +708,7 @@ void pack_sram(Context *ctx)
std::unique_ptr<CellInfo> ramw_slice =
create_generic_cell(ctx, id_RAMW, ci->name.str(ctx) + "$RAMW_SLICE");
sram_to_ramw_split(ctx, ci, ramw_slice.get());
ramw_slice->connectPort(id_CE, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
// Create actual RAM slices
std::unique_ptr<CellInfo> ram_comb[4];