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1280 Commits

Author SHA1 Message Date
Eddie Hung daedf73291 Use new Arch::isIOCell() function in Timing 2018-08-06 12:12:03 -07:00
Eddie Hung 21cd1d7dd6 Add new Arch::isIOCell() API function 2018-08-06 12:11:47 -07:00
Eddie Hung 3f5c0373a5 Consider clocked cells with COUT, consider constant nets 2018-08-06 12:03:58 -07:00
Eddie Hung 266b761f41 Merge branch 'fix_budget_overrides' into assign_budget_speedup 
Conflicts:
	common/timing.cc
 2018-08-06 09:02:49 -07:00
Eddie Hung c9141262b2 Modify doc 2018-08-06 08:39:11 -07:00
Eddie Hung 8e8ba0293c Fix use of getBudgetOverride in Timing::follow_net() 2018-08-06 08:34:37 -07:00
Eddie Hung 0f3459dbe5 Fix ice40's getBudgetOverride() to override only for COUT -> CIN 2018-08-06 08:22:08 -07:00
Eddie Hung d0312514bd Modify getBudgetOverride for generic and ecp5 too 2018-08-06 07:56:34 -07:00
Eddie Hung 823ceaacbf Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-06 07:56:28 -07:00
Eddie Hung 665202e936 Merge branch 'assign_budget_evenly' into assign_budget_speedup 
Conflicts:
	common/timing.cc
 2018-08-06 07:35:00 -07:00
Eddie Hung 2fb934b107 clangformat 2018-08-06 07:19:32 -07:00
Eddie Hung fa773c3ce9 Add net_delays bool to Timing class to control net delay consideration 2018-08-06 07:18:06 -07:00
Eddie Hung 9b414594d2 Unless slack_redist is enabled, ignore net delays so that budget gets evenly divided between all nets on path 2018-08-05 23:00:15 -07:00
Eddie Hung f048deb33d Restore initial assign_budget() call after pack(), restrict call after initial_placement to slack_redist 2018-08-05 22:55:58 -07:00
Eddie Hung e314ea761a WIP for new assign_budget() using topographical ordering 2018-08-05 22:38:54 -07:00
Eddie Hung 8a6ff4b261 Modify getBudgetOverride for generic and ecp5 too 2018-08-05 22:33:14 -07:00
Eddie Hung 7aab4925b4 Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-05 22:31:59 -07:00
Clifford Wolf 6c8319e29a
Merge pull request #37 from YosysHQ/ngapi 
API change: Use CellInfo* and NetInfo* as cell/net handles
 2018-08-05 16:46:24 +02:00
David Shah b3acd8095f timing: Fix slack histogram segfault with no paths 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:36:35 +02:00
David Shah 736f2a0717 API change: Use CellInfo* and NetInfo* as cell/net handles (ECP5) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:32:12 +02:00
David Shah 1ce0b5add2 API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:21:13 +02:00
Clifford Wolf 2853149c68 API change: Use CellInfo* and NetInfo* as cell/net handles (archapi docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:39:44 +02:00
Clifford Wolf c3c9dab9f7 API change: Use CellInfo* and NetInfo* as cell/net handles (generic) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:34:16 +02:00
Clifford Wolf 5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
David Shah ba97c233fb
Merge pull request #36 from YosysHQ/lutperm 
Add LUT input permutations, improvements in ice40 timing model, improvements in router
 2018-08-05 14:31:43 +02:00
Clifford Wolf 287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
Eddie Hung 8a9b3626d3
Merge pull request #31 from eddiehung/slack_histogram 
Print slack histogram at end of placement and at end of routing
 2018-08-05 00:03:18 -07:00
Eddie Hung 8974ef3327 Slack histogram to use ps granularity via int(Arch::getDelayNS() * 1000) 2018-08-04 18:55:03 -07:00
Eddie Hung 76a7d67f74 Revert "Be cognisant that delay_t could be a non-integer type (if so, truncate to integer)" 
This reverts commit b07f0eebc8.
 2018-08-04 18:54:23 -07:00
Eddie Hung b07f0eebc8 Be cognisant that delay_t could be a non-integer type (if so, truncate to integer) 2018-08-04 18:47:42 -07:00
Eddie Hung aebb39c651 Merge branch 'master' into slack_histogram 2018-08-04 18:40:37 -07:00
Clifford Wolf 528eddcaf7 Fix bug in ice40 estimateDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 22:29:43 +02:00
Clifford Wolf d31036825b Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 20:17:46 +02:00
Clifford Wolf 175da732ac Use faster model for ice40 predictDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 20:16:43 +02:00
Clifford Wolf f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00
David Shah 67347573c2 ice40: Bitstream gen for LUT permutation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 18:23:48 +02:00
Clifford Wolf 8aaf845670 Quick fix for router bug in unrouting a conflicting pip 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 17:23:46 +02:00
Clifford Wolf 31fe52581b Add generation of models to tmfuzz 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 16:54:12 +02:00
Miodrag Milanovic 7d5dba3ad3 compile fix 2018-08-04 16:27:33 +02:00
Clifford Wolf bd36cc1275 Refactor ice40 timing fuzzer used to create delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:41:42 +02:00
Clifford Wolf 700e68746a Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:33:24 +02:00
Miodrag Milanović dc34d4c9ed
Merge pull request #33 from YosysHQ/gui-ecp5 
Gui ecp5
 2018-08-04 04:05:38 -07:00
Clifford Wolf af74f6e511 Add router1 cfg.useEstimate, improve getActualRouteDelay 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 11:57:34 +02:00
Miodrag Milanovic 0cb349b60e Utility calls static 2018-08-04 11:54:34 +02:00
Clifford Wolf 086bc941a8 Remove SVG functionality from ice40 main 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 11:52:35 +02:00
Miodrag Milanovic dc4bd1b55f Move ArchArgs to BaseWindow 2018-08-04 11:52:07 +02:00
Miodrag Milanovic a31c00ed96 Chip selection ui for ECP5 2018-08-04 11:48:29 +02:00
Miodrag Milanovic beb5f9d4df not needed anymore 2018-08-04 11:37:41 +02:00
Miodrag Milanovic 17f461ed4f add write bitstream 2018-08-04 11:21:38 +02:00
Clifford Wolf 96291f17aa Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 10:32:07 +02:00