Commit Graph

2312 Commits

Author SHA1 Message Date
Miodrag Milanovic d5174110fa more pips on connection box 2019-12-15 10:57:24 +01:00
Miodrag Milanovic f2b8e347a9 cleanup and formating 2019-12-15 10:43:30 +01:00
Miodrag Milanovic 2872b500e3 make it more simetric 2019-12-15 10:33:12 +01:00
Miodrag Milanovic bbc05f3113 optimize and add some missing pips 2019-12-15 10:07:55 +01:00
Miodrag Milanovic 3d42097e9d cleanup 2019-12-15 09:45:09 +01:00
Miodrag Milanovic fa55a826b2 cleanup wire 2019-12-15 09:26:25 +01:00
Miodrag Milanovic 436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic cce27e72f0 lot more pips 2019-12-14 16:29:25 +01:00
Miodrag Milanovic abf9bc3bb9 fixes and more pips 2019-12-14 16:10:41 +01:00
Miodrag Milanovic d42ecc081e pips for alu, mult and memory 2019-12-14 13:00:09 +01:00
Miodrag Milanovic 7e7e20742d pips for ios 2019-12-14 12:30:04 +01:00
Miodrag Milanovic 601360b73a propagate w and h 2019-12-14 10:56:26 +01:00
Miodrag Milanovic e118e418e5 pips for other type of connection box 2019-12-14 09:39:41 +01:00
Miodrag Milanovic ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic 19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic 6d005f38b5 add more 2019-12-13 19:44:49 +01:00
Miodrag Milanovic 2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic 16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic 7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic 275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic 401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic 76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
Miodrag Milanovic 0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
Miodrag Milanovic da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic 2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic 522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic 6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic 74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic 43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic 9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
Miodrag Milanovic 49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
Miodrag Milanovic 0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic 847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00