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33 Commits

Author SHA1 Message Date
José Miguel Sánchez García 1d4b0eeac4
himbaechel: xilinx: misc `CMakeLists.txt` improvements (#1509) 
* himbaechel: xilinx: replace `/usr/bin/pypy3` with `${Python3_EXECUTABLE}`

* himbaechel: xilinx: recognize `IMPORT_BBA_FILES` inside `CMakeLists.txt`

* himbaechel: xilinx: align CMake device selection behavior with gatemate
 2025-07-02 14:58:09 +02:00
myrtle 27635785c8
heap: Allow customising legalisation ordering (#1507) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-07-01 15:32:28 +02:00
gatecat 1cd1e4a8d9 xilinx: Fix packing of weird mux trees 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 12:38:11 +02:00
gatecat 226a2dfdb4 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-20 13:19:52 +02:00
Catherine 90d746f79e CMake: add support for exporting and importing .bba files. 
This is useful for certain cross-compilation workloads, and to cache
rarely changing build products.

To use this functionality, build e.g. as follows:

    cmake . -B build-export -DEXPORT_BBA_FILES=../bba-files -DARCH=all
    cmake --build build-export -t nextpnr-all-bba

    cmake . -B build-import -DIMPORT_BBA_FILES=../bba-files -DARCH=all
    cmake --build build-import
 2025-01-23 07:49:12 +00:00
Catherine cd7f7c12f1 CMake: refactor architecture-specific build system parts. 
Two user-visible changes were made:
* `-DUSE_RUST` is replaced with `-DBUILD_RUST`, by analogy with
  `-DBUILD_PYTHON`
* `-DCOVERAGE` was removed as it doesn't work with either modern GCC
  or Clang
 2025-01-21 17:13:03 +00:00
Catherine dcfb7d8c33 CMake: align Himbaechel targets with non-Himbaechel ones. 
Primarily, this commit makes both of them use the `BBAsm` functions
to build and compile `.bba` files.

In addition, Himbaechel targets are now aligned with the rest in
how they are configured: instead of having all uarches enabled with
all of the devices disabled (the opposite of the rest of nextpnr),
uarches must be enabled explicitly but they come with all devices
enabled (except for Xilinx, which does not have a list of devices).
 2025-01-21 17:13:03 +00:00
Catherine d214308f5f CMake: reformat for consistency. 
Normalize keywords to:

    if (...)
    elseif (...)
    else()
    endif()

    foreach (...)
    endforeach()

    other(...)

Normalize whitespace to 4 spaces.
 2025-01-16 11:36:44 +01:00
Catherine 5fe680390f
Various fixes for clang/libc++ build (#1415) 
* Gowin: add header includes required on libstdc++.

* kernel: fix incorrect printf-style format.

* himbaechel: add missing `override` qualifiers.

* Gowin: remove unnecessary `std::move`.

These calls inhibit RVO, a stronger optimization than moving an object.
 2025-01-12 08:11:33 +01:00
Adrien Prost-Boucle 7f33329fe1 Himbaechel Xilinx : XDC commands : Also search nets with lowercase for better interoperability with other synthesis tools and RTL languages 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle 3d00b97e0a Himbaechel Xilinx : Support get_nets with braces around net name in XDC commands 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle a9cc7f453d Himbaechel Xilinx : Support multiple nets per command 2024-10-01 15:24:40 +02:00
Adrien Prost-Boucle ff9ba9e090 Himbaechel Xilinx : More warning messages about unsupported things in XDC file 2024-10-01 15:24:40 +02:00
gatecat 1967db170d xilinx: Support for complex IOLOGIC 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:37:46 +02:00
gatecat 24fc33c014 xilinx: Basic I/ODDR support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:09:15 +02:00
gatecat d3c0f945da xilinx: Fix BRAM placement, clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:24:47 +02:00
gatecat 38e5faca85 xilinx: Fix workaround for unsupported xdc construct 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:07:38 +02:00
gatecat e4dfd4e622 xilinx: Support single-port LUTRAM variants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 18:11:01 +02:00
gatecat 7516b8950a xilinx: Few more stub timings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 17:30:36 +02:00
gatecat 118ecbc6b3 xilinx: Remove unnecessary assert 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:58:16 +02:00
gatecat c90d872e35 xilinx: Filter out another missing pip type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:56:20 +02:00
Adrien Prost-Boucle 437fb70ed3 Himbaechel xilinx : Fix packing of cascaded DSP 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 9da05b6001 Himbaechel xilinx : DSP packing : Emit a non-fatal error message 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 2031a067a0 Himbaechel xilinx : More flexibility about types of DSP parameters 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 81bf92a855 Himbaechel xilinx : DSP packing : Disable clustering 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 8a0e062520 Himbaechel xilinx : DSP packing : Improve code efficiency 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 9bea22ed1e Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle ad9a54cc69 Himbaechel xilinx : More cascaded input ports for which routing is skipped 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle 04f5f80766 Himbaechel xilinx : Add safety check in DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle db0c99199e Himbaechel xilinx : Add support of DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle fa55e93848 Himbaechel xilinx : Fix regex to parse Zynq device names 2024-08-19 21:06:45 +01:00
gatecat e2a887ef0d himbaechel: Switch default back to router1 for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:09:59 +01:00
gatecat 5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00