* Gowin. BUGFIX. BSRAM SP separation.
The new SP cell must inherit the byte size - 8 or 9 bits.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Byte Enables processing in SP.
Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.
With the advent of byte enable support, it became necessary to switch
these signals differently.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This connection is implicit as it is hardwired in the hardware.
This commit makes the connection explicit and thus appearing in the
generated netlist allowing post-rout simulation.
The TLVDS_IBUF_ADC IO primitives have been implemented, which provide a
signal for ADC bus 2. These differential IO primitives also have an
additional input that allows them to be disabled, thereby providing
dynamic switching of the signal source for the ADC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
ADC support for GW5A-25 chips has been added.
The inputs of this primitive are fixed and do not require routing,
although they can be switched dynamically.
The .CST file also specifies the pins used as signal sources for the
bus0 and bus1 ADC buses.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: handle default parameters for IO
This is probably a VHDL specific issue. In VHDL, there is no
black-box. Primitive instantiations are done using VHDL component
instantiations and the component must have been declared with all its
ports and parameters (generic). Currently the components are
translated from cells_sim.v and cells_bb.v
If a user doesn't override a parameter, the default value is used
instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER
or SLEW parameters of CC_IOBUF. I think this is a main difference
with verilog, where unspecified parameters do not appear.
With this change, the UNPLACED value of PIN_NAME and UNDEFINED value
of DRIVE are simply ignored.
* gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW
Since ctx->getArchArgs() no longer returns architecture-specific
arguments, we read the args field directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: Use GATEMATE_DIE attribute to select placement die
* add DIE parameter in CCF
* add penalty delay when crossing between dies
* Add predictDelay
* Use QtPropertyBrowser for Qt5/6
* Fix cmake for python-console for consistency
* Make GUI compile for both Qt5 and Qt6
* Fix crash on init with Wayland on Qt6
* Cleanup
* disable deprecation warnings for now
* Relaxed cmake check for initial Qt6 test
In the GW5A series, the primitive SemiDual Port BSRAM cannot function
when the width of any of the ports is 32/36 bits - it is necessary to
divide one block into two identical ones, each of which will be
responsible for 16 bits.
Here, we perform such a division and, in addition, ensure that the new
cells resulting from the division undergo the same packing procedure as
the original ones.
Naturally, with some reservations (the AUX attribute is responsible for
this) - in the case of SP, when service elements are added, it makes
sense to do this immediately for 32-bit SP and only then divide.
Also, SDPs are currently being corrected for cases where both ports are
‘problematic’, but it may happen that one port is 32 and the other is,
say, 1/2/4/8/16. This has been left for the future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the chipdb is not found, the Setup() call throws, but GTest still calls
TearDown, which then stumbles over the uninitialized pointer.
This makes the tests fail without valgrind errors or segfaults at least.
In the new series of chips, the SemiDual Port primitive has one RESET
pin instead of two in previous versions - RESETA and RESETB.
Physically, the two pins are still there and both must be connected,
with RESETA being constant.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Over time, it became clear that the special status of corner tiles is
handled in other parts of the toolchain, and in the GW5A chip series, it
began to interfere—in this series, IO can be located in the corners.
So we move the only function (creating VCC and GND) to the extra
function itself, and at the same time create a mechanism for explicitly
specifying the location of these sources in Apicula when necessary.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Lofty
Miodrag Milanovic
YRabbit
Robert Ward
TG
Patrick Urban
tgingold
myrtle
egorxe
Gwenhael Goavec-Merou
Simon Richter