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4653 Commits

Author SHA1 Message Date
SpaceCat-Chan a7e25754e1 make pip exploration not cursed 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 8e66d3d7d8 add uphill pips iter 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 1c0885435c make find_best_pip take an arc instead of wires 2023-12-06 17:52:37 +00:00
SpaceCat-Chan fe5daebba5 improve partition sanity check quality of life 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 38908e64fb use new arc type in partitioner 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 88f88e48cb only search pips inside partition bounds 2023-12-06 17:52:37 +00:00
Lofty 686648c406 awooter: wip 2023-12-06 17:52:37 +00:00
SpaceCat-Chan d64289da65 finalize downhill iterator 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 0c647c0471 create downhill iter wrapper 2023-12-06 17:52:37 +00:00
Lofty 0aadeab542 awooter: further clean up 2023-12-06 17:52:37 +00:00
Lofty 063c96c3df awooter: add Arc struct 2023-12-06 17:52:37 +00:00
SpaceCat-Chan b50e56a543 split partitioning code into seperate file 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 862fbf7ca7 split arc extraction into function 2023-12-06 17:52:37 +00:00
Lofty 6279d1642c awooter: clean up unused code 2023-12-06 17:52:37 +00:00
Lofty fbbcf6aa67 awooter: return of the progress bar 2023-12-06 17:52:37 +00:00
SpaceCat-Chan d7dbaa2c7e fix bug in split_line_over_x 2023-12-06 17:52:37 +00:00
Lofty b4a442ba29 awooter: simple time measurement 2023-12-06 17:52:37 +00:00
SpaceCat-Chan 0a46c5b491 make partitioner run in parallel over nets 2023-12-06 17:52:37 +00:00
Lofty 3931daefc7 awooter: atomics instead 2023-12-06 17:52:37 +00:00
Lofty 1b80a559e2 awooter: better locking 2023-12-06 17:52:37 +00:00
Lofty 026c2883e5 awooter: properly parallelise 2023-12-06 17:52:37 +00:00
Lofty 937acd3ee9 awooter: clamp pip indices 2023-12-06 17:52:37 +00:00
Lofty 49b6d894d1 awooter: cargo fmt 2023-12-06 17:52:37 +00:00
Lofty 8276bf255d awooter: parallelise partitioning 2023-12-06 17:52:37 +00:00
Lofty ac43ddbcc5 awooter: refactor and bugfix 
Co-authored-by: Spacecat-Chan <49094338+SpaceCat-Chan@users.noreply.github.com>
 2023-12-06 17:52:37 +00:00
Lofty 5d74f340dd awooter: further prettify 2023-12-06 17:52:37 +00:00
Lofty 94c921a48e awooter: prettify 2023-12-06 17:52:37 +00:00
Lofty 9a2532be45 awooter: net-based partitioner 2023-12-06 17:52:37 +00:00
Lofty 95e802ee3d awooter: wire storage and some cleanup 2023-12-06 17:52:37 +00:00
Lofty 153c8a9c6c awooter: 'better' FFI API 2023-12-06 17:52:37 +00:00
Lofty d27bcbf19e awooter: fix an API soundness issue 2023-12-06 17:52:37 +00:00
Lofty 2662354aae awooter: partition experiment code 2023-12-06 17:52:37 +00:00
Lofty c821a68da7 awooter: add net import code 2023-12-06 17:52:37 +00:00
Jubilee a579b5852a Specify PROFILE when importing awooter 
Otherwise CMake and Corrosion get confused about how to put things together.
 2023-12-06 17:52:37 +00:00
Lofty 8052a3eea6 awooter: highly, highly WIP 2023-12-06 17:52:37 +00:00
gatecat 6d9322457e static: Reduce stddev of initial solution 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-26 16:51:47 +01:00
YRabbit c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit 90d4863dd4 gowin: Himbaechel. Add GW1NZ-1 BSRAM. 
The following primitives are implemented for the GW1NZ-1 chip:

* pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9   - read only memory - (bitwidth: 9, 18, 36).
* SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
* DPB      - dual port        - (bitwidth: 16).
* DPX9B    - dual port        - (bitwidth: 18).
* SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9     - single port      - (bitwidth: 9, 18, 36).

Also:
 - The creation of databases for GW1NS-2 has been removed - this was not
   planned to be supported in Himbaechel from the very beginning and
   even examples were not created in apicula for this chip due to the
   lack of boards with it on sale.
 - It is temporarily prohibited to connect DFFs and LUTs into clusters
   because for some reason this prevents the creation of images on lower
   chips (placer cannot find the placement), although without these
   clusters the images are quite working. Requires further research.
 - Added creation of ALU with mode 0 - addition. Such an element is not
   generated by Yosys, but it is a favorite vendor element and its
   support here greatly simplifies the compilation of vendor netlists.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit f2c280feda gowin: Himbaechel. Initial BSRAM support 
Only pROM/pROMX9 for now

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
Miodrag Milanovic e3f4578b3b CRLF -> LF eol 2023-11-23 09:22:07 +01:00
Miodrag Milanovic ec60542ffd create wiremap for himbaechel arch 2023-11-23 09:22:07 +01:00
Miodrag Milanovic 1ec8e411d7 set render bound box, so grid is displayed 2023-11-23 08:21:26 +01:00
Miodrag Milanovic 0b8a93eed5 fix compile warning 2023-11-23 08:21:26 +01:00
gatecat de3d5be8f0 python: Remove deprecated use of Py_SetProgramName 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-23 06:49:15 +01:00
Balint Cristian 7814f44883 Fix abstract class implementation for fpga_interchange 
Signed-off-by: Balint Cristian <cristian.balint@gmail.com>
 2023-11-23 06:49:01 +01:00
gatecat 6683fd4ada himbaechel: Fix when more then 32k unique node shapes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-22 17:11:27 +01:00
gatecat 55635cf2cd Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:14:19 +01:00
gatecat e2a887ef0d himbaechel: Switch default back to router1 for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:09:59 +01:00
gatecat 5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00
laanwj a32ad13a86 ecp5: Don't segfault while packing FFs when DI port of TRELLIS_FF unconnected 
Currently a segfault happens when the DI port is not specified. Leaving
it unconnected is probably incorrect, but it shouldn't crash the placer.
Fix by adding a check.
 2023-11-14 11:55:51 +01:00