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9dce00a4e7b9bdaf1b2bbc0c9d8c2ccc830c65b1
Commit Graph
1060 Commits
Author SHA1 Message Date
gatecat 5a41d2070c Run clangformat 
Signed-off-by: gatecat <[email protected]>
 2021-05-16 16:25:05 +01:00
gatecat 3bb94192d5 mistral: Tidying up 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat f318898474 router2: Hacky workaround for slow Cyclone V convergence 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat 511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat e5e2f7bc62 mistral: Add stub pack/place/route functions 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat b1d3eb07c3 archcheck: Use old connectivity check for CycloneV 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat 5d1b8bf744 cyclonev: Add names and archcheck fixes 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 14:54:33 +01:00
gatecat ee60e9c71c router2: Add some boundness statistics 
Signed-off-by: gatecat <[email protected]>
 2021-05-12 12:18:58 +01:00
gatecat e9fdbf618c router2: Fix a typo 
Signed-off-by: gatecat <[email protected]>
 2021-05-11 13:02:23 +01:00
gatecat b3b79122e1 command: Allow debug output for just placer or router 
Signed-off-by: gatecat <[email protected]>
 2021-05-11 11:35:43 +01:00
gatecat 65c611da02 router2: Reserve wires in more complex cases 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 21:20:09 +01:00
gatecat 62613cb266 router2: Dynamicly expand bounding box based on congestion 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 19:04:24 +01:00
gatecat 0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 13:12:52 +01:00
gatecat 1bf202adcd base_arch: Fix typo in getClusterPlacement 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 12:23:28 +01:00
gatecat 14863bc04e Update placers to use new cluster APIs 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 11:47:07 +01:00
gatecat 6a3eacddd6 Add default base implementation of cluster API 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 11:47:06 +01:00
gatecat e1717bd771 Add BaseClusterInfo for base implementation 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 11:47:06 +01:00
gatecat b62dcc4bcc arch_api: Outline of new cluster API 
Signed-off-by: gatecat <[email protected]>
 2021-05-06 11:47:06 +01:00
David Corrigan f5c2547952 Update bits.h 
Fixed the variable name for windows MSVC builds.
 2021-04-30 21:42:25 -05:00
gatecat dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <[email protected]>
 2021-04-30 11:07:31 +01:00
gatecat 6fbefb8f13 Merge pull request #681 from YosysHQ/gatecat/more-pybindings 
Add Python bindings for placement tests
 2021-04-15 11:16:31 +01:00
gatecat d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <[email protected]>
 2021-04-15 10:00:45 +01:00
gatecat d14db5c98f Fix utilisation report when bel buckets are used 
Signed-off-by: gatecat <[email protected]>
 2021-04-15 09:24:27 +01:00
gatecat 4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <[email protected]>
 2021-04-14 10:30:19 +01:00
gatecat ece10c3e04 timing: Fix domain init when loops are present 
Signed-off-by: gatecat <[email protected]>
 2021-04-13 09:23:08 +01:00
gatecat 5cd2a7f9c2 Merge pull request #674 from adamgreig/heap-spreader-fix 
HeAP: Skip high-strength cells in both cell loops
 2021-04-12 14:16:22 +01:00
Adam Greig 2fdf41ac01 HeAP: Skip high-strength cells in both cell loops. 
Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
 2021-04-12 13:42:20 +01:00
gatecat 5b35329abb fast_bels: Don't return pointer that might become invalid 
Signed-off-by: gatecat <[email protected]>
 2021-04-12 10:23:41 +01:00
Keith Rothman a519341112 Fix bug in router2 where router may give up too early. 
Was introduced in #612.  The logic before was intended to prevent the
router from terminating early when not using a bounding box, but the fix
in #612 simply removed that, meaning that the router might terminate
early incorrectly.  The solution here is to only use the toexplore
hysteric once a solution is found.

Signed-off-by: Keith Rothman <[email protected]>
 2021-04-06 10:22:47 -07:00
gatecat 8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <[email protected]>
 2021-03-30 15:28:19 +01:00
Keith Rothman 77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-25 17:20:09 -07:00
Keith Rothman 8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-23 09:01:43 -07:00
gatecat e8d36bf5bd Merge pull request #634 from litghost/add_get_bel_pin_type 
Add getBelPinType to Python interface.
 2021-03-22 18:31:48 +00:00
Keith Rothman 4cd74bba2c Add getBelPinType to Python interface. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-22 09:25:45 -07:00
Keith Rothman e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <[email protected]>
 2021-03-22 09:17:55 -07:00
Keith Rothman 2cd5bacca0 Refactor header structures in FPGA interchange Arch. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-19 21:36:06 -07:00
Keith Rothman a3dd5b33bc Run "make clangformat". to fix up master. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-18 13:30:37 -07:00
Keith Rothman 965ba00e0f Moving hash map/set type selection to header. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-17 16:54:29 -07:00
whitequark e1cd98ba15 Add missing includes to fix WASI build. 2021-03-16 05:52:41 +00:00
Keith Rothman 351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-15 18:49:12 +00:00
gatecat a8e35062c6 Merge pull request #621 from litghost/fix_header_nightmare 
Split nextpnr.h to allow for linear inclusion.
 2021-03-15 17:00:52 +00:00
gatecat 3c71911c26 opt-timing: Skip undriven nets 
Signed-off-by: gatecat <[email protected]>
 2021-03-15 16:08:47 +00:00
Keith Rothman fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <[email protected]>
 2021-03-15 09:05:23 -07:00
Keith Rothman a342ae56e0 Add support for partially routed nets from the placer in router2. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-12 09:53:15 -08:00
Keith Rothman 7168cf8657 Add diagnostic prints to debug lookahead performance. 
Signed-off-by: Keith Rothman <[email protected]>
 2021-03-10 09:12:50 -08:00
whitequark 979e7b8709 Only depend on Abseil in threaded builds. 
Abseil has a hard dependency on threads (not just in the build system
but in many places in the base libraries), so there is no way to use
it on WASI at the moment.
 2021-03-10 06:18:42 +00:00
gatecat d1f44fe91a Merge pull request #607 from litghost/add_absl_flat_hash_map 
Add absl::flat_hash_map.
 2021-03-09 08:48:25 +00:00
gatecat 326b34887c Merge pull request #609 from YosysHQ/gatecat/sta-v2 
Use new timing engine for criticality
 2021-03-09 08:48:12 +00:00
gatecat da88d3d825 router2: Fix vast perf drop when leaving bounding box 
Signed-off-by: gatecat <[email protected]>
 2021-03-08 15:06:30 +00:00
gatecat 8a4bf3a780 timing: Integration tweaks 
Signed-off-by: gatecat <[email protected]>
 2021-03-05 10:04:35 +00:00