Commit Graph

5 Commits

Author SHA1 Message Date
gatecat fcc1a33f75 xilinx: Derive clock constraints through PLLs
Signed-off-by: gatecat <gatecat@ds0.me>
2026-03-24 14:08:37 +01:00
gatecat 4ace8952d3 xilinx: Support cascaded IOSERDES and TMDS
Signed-off-by: gatecat <gatecat@ds0.me>
2026-03-05 13:59:35 +01:00
gatecat 0cd6e72d5f xilinx: Add MMCM support
Signed-off-by: gatecat <gatecat@ds0.me>
2026-02-21 20:17:34 +01:00
Adrien Prost-Boucle 8a0e062520 Himbaechel xilinx : DSP packing : Improve code efficiency 2024-09-24 12:06:56 +02:00
gatecat 5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray
Signed-off-by: gatecat <gatecat@ds0.me>
2023-11-14 17:12:09 +01:00