2da7caf657
Merge pull request #993 from yrabbit/lw-wip-1
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gowin: Add support for long wires
2022-06-07 13:09:09 +01:00
db696af2fe
gowin: Add support for long wires
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Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-05-27 22:44:21 +10:00
997af6d720
Merge pull request #992 from antmicro/mdudek/nexus_write_dcc
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Change write_dcc to work with tilegroups from prjoxide
2022-05-27 10:13:15 +01:00
8c4e3e91cc
Change write_dcc to work with tilegroups from prjoxide
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-05-27 10:58:39 +02:00
48f9daf867
Merge pull request #990 from YosysHQ/gatecat/fix-988
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Don't assert on mixed domain paths in report
2022-05-22 14:31:55 +01:00
447b5b905c
Don't assert on mixed domain paths in report
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-05-22 13:56:36 +01:00
e900494394
Merge pull request #989 from YosysHQ/lofty/cmake-bump
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Bump minimum CMake to 3.13
2022-05-21 19:26:30 +01:00
ae67c98f11
Bump minimum CMake to 3.13
2022-05-21 18:26:36 +01:00
4ecbf6c6e9
Merge pull request #985 from antmicro/interchange-lut-constants
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[interchange] Tying unused LUT inputs according to architecture
2022-05-13 09:09:50 +01:00
d75c45c63f
Added fallback to VCC as the preferred constant if the architecture does not specify one.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-05-12 11:55:16 +02:00
7c7a4f0959
Added tying unused LUT pins to preferred constant instead of Vcc
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-05-11 16:31:34 +02:00
aafe1a176c
Generalized representation of unused LUT pins connections
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-05-11 16:31:30 +02:00
41936fefac
Merge pull request #984 from yrabbit/assert
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common: Correct a minor typo in the message
2022-05-10 13:17:22 +01:00
1aa693732c
common: Correct a minor typo in the message
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-05-10 21:19:02 +10:00
769a1f263a
Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fix
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ice40: Fix propagation of constraints through SB_GB
2022-05-08 13:37:53 +01:00
27966f101f
ice40: Fix propagation of constraints through SB_GB
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-05-08 12:44:03 +01:00
a494982646
Merge pull request #981 from yrabbit/lw-cst-0
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gowin: Add initial syntax support for long wires
2022-05-03 17:52:02 +01:00
15413de359
gowin: Add initial syntax support for long wires
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Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-05-02 20:40:33 +10:00
f0d4e4fbc3
generic: Add some extra helpers for viaduct uarches
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-05-02 11:02:09 +01:00
20cfafa109
generic: Add missing uarch guard
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-27 14:18:42 +01:00
a35c80cc10
ecp5: Tweak delay prediction
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-20 11:29:08 +01:00
b8f9f2daa2
Merge pull request #977 from YosysHQ/gatecat/prefine-tileswap
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prefine: Do full-tile swaps, too
2022-04-19 19:09:29 +01:00
19cade3b3b
prefine: Do full-tile swaps, too
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-19 18:37:16 +01:00
d76a6093ae
Merge pull request #976 from YosysHQ/gatecat/dp-rework
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Move general parallel detail place code out of parallel_refine
2022-04-17 20:33:15 +01:00
61b3e2e1ff
Move general parallel detail place code out of parallel_refine
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-17 20:10:49 +01:00
895aa01e39
Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fix
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ice40: Avoid chain finder from mixing up chains by only allowing I3 c…
2022-04-12 14:27:36 +01:00
d3ba259db2
ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining at end
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-11 18:46:44 +01:00
9067d954f4
Merge pull request #974 from YosysHQ/gatecat/ci-restructure
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ci: Restructure and move entirely to GH actions from Cirrus
2022-04-08 19:51:46 +01:00
92a58a2631
ci: Restructure and move entirely to GH actions from Cirrus
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-08 18:42:39 +01:00
57681e69ce
Merge pull request #973 from YosysHQ/gatecat/folder-tidy
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Split up common into kernel,place,route
2022-04-08 14:32:33 +01:00
49f178ed94
Split up common into kernel,place,route
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-08 13:42:54 +01:00
e42e22575f
Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2
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ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
2022-04-07 18:43:25 +01:00
efb58711b0
ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
2022-04-07 18:02:36 +01:00
d5ec421d98
Merge pull request #971 from modwizcode/fix-tbb-macos
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cmake: properly include TBB libraries.
2022-04-06 10:40:20 +01:00
03074cdbc2
cmake: properly include TBB libraries.
2022-04-05 10:12:44 -05:00
c4e47ba1a8
generic: Allow bel pins without wires
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-04 19:49:44 +01:00
fcf2bf6a95
Merge pull request #970 from yrabbit/nr9-wip
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gowin: handle the GW1N-9 feature.
2022-04-03 11:40:50 +01:00
85e8570a73
gowin: handle the GW1N-9 feature.
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This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-04-03 10:05:27 +10:00
2ed68a21db
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-31 10:49:00 +01:00
219310b203
Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fix
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ice40: Fix wirenames containing / which is the list separator
2022-03-31 06:45:54 +01:00
336124b879
ice40: Fix wirenames containing / which is the list separator
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-30 20:57:00 +01:00
e96ec9a102
Merge pull request #968 from tpambor/gowin-osc-fix
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gowin: Fix z-index of oscillator
2022-03-30 18:57:54 +01:00
601b32948b
gowin: Fix z-index of oscillator
2022-03-30 17:35:54 +02:00
5850cb6336
Merge pull request #952 from antmicro/mdudek/nexus_pll
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Nexus: Fixed OSCA parameters, add pll default parameters
2022-03-30 15:39:10 +01:00
b9e76d1bcd
Rename parse_lattice_param to parse_lattice_param_from_cell
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Add new definition for parse_lattice_param
Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-03-30 14:59:47 +02:00
84c5b578d4
Merge pull request #966 from YosysHQ/gatecat/ice40-opt
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ice40: Merge driving LUT<=2s into carry-only LCs
2022-03-29 15:20:45 +01:00
6f6b502f7a
Merge pull request #960 from YosysHQ/gatecat/viaduct-docs
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First pass viaduct docs
2022-03-29 14:06:23 +01:00
bd81dcc8f9
Merge pull request #965 from tpambor/gowin-osc
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gowin: Add bels for oscillator
2022-03-29 13:57:40 +01:00
5a9ddc0675
ice40: Merge driving LUT<=2s into carry-only LCs
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-29 13:37:14 +01:00
12b38bab6d
gowin: Add bels for oscillator
2022-03-27 22:15:12 +02:00
myrtle
YRabbit
Maciej Dudek
Lofty
Maciej Kurc
Irides
Tim Pambor