luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,009 Commits 30 Branches 9 Tags 27 MiB
Commit Graph

5009 Commits

Author SHA1 Message Date
Miodrag Milanovic e1ba78094f gatemate: clean data bitmask 2025-08-27 12:28:58 +02:00
Miodrag Milanovic 8ab9301dc4 clangformat 2025-08-27 10:37:39 +02:00
Miodrag Milanovic 2b203d21ae gatemate: add missing RAM port mapping 2025-08-27 10:37:10 +02:00
YRabbit 52254dca35
Gowin. Add ROM16 primitive. (#1542) 
The LUTRAM mode is added to all supported chips at once.

This is essentially an alias for LUT4, so the packaging is also moved
before searching for LUT-DFF pairs for possible optimization.

In addition to being the only LUTRAM mode in the GW5A series, the
addition of ROM16 eliminates the need to manually rename the primitive
and its pins when working with files generated by Gowin IDE - a similar
situation occurred with INV, which is essentially LUT1.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-27 07:21:38 +02:00
YRabbit d966fc5dcb
Gowin. Implement ALU for the GW5A series. (#1541) 
The ALUs in the GW5A series have undergone changes compared to previous
chips.

The most significant change is the appearance of an input MUX for
carry — it is now possible to switch between VCC, GND, and COUT of the
previous ALU, as well as generate carry in logic.

The granularity of resource allocation for ALUs has also changed — it is
now possible to use each half of a slice independently for ALUs.

Not all new features are reflected in this commit:

  - since there is one CIN MUX for every six ALUs and it only works for
    ALUs with index 0, the new granularity is not very useful: the head of
    the chain can only be placed in the zero ALU. It is possible to gain one
    LUT by allocating ALUs in odd numbers, but we will leave that for the
    future.

  - using CIN MUX to generate carry in logic is interesting, but we have
    not yet been able to get the vendor IDE to generate such a
    configuration to figure out which wires are used, so for now we are
    leaving the old behavior in logic with the allocation of a specialized
    head ALU.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-26 16:17:55 +02:00
Lofty 0a7cbe1cd7
router2: iteratively reserve arc driver wires, too (#1539) 2025-08-26 16:17:11 +02:00
Miodrag Milanovic ca4f727ffc gatemate: fix CI/CO RAM connections 2025-08-25 12:24:46 +02:00
Miodrag Milanovic 84234e7d79 gatemate: delay, assign proper RAM clock 2025-08-25 10:55:19 +02:00
Miodrag Milanovic d796cc720b clangformat 2025-08-22 11:08:39 +02:00
Miodrag Milanović 6a598b945e
gatemate: add iopath delays (#1537) 
* Timing

* clangformat

* Import some new data

* Import all timing data

* Add constants for needed timings

* Add separate file for delay handling

* wip

* Added helpers

* wip

* proper place for assignArchInfo

* wip

* wip

* Fixes for IO

* Add IOSEL delays

* Fix logic loops

* help figure out some ram paths

* return true only if exists

* cover all primitives

* Disable not used paths

* clockToQ

* Added some RAM timings

* Add more IOPATHs

* cleanup

* cleanup

* Map few more timings

* remove short name options

* support strings as options

* no need for return
 2025-08-22 11:07:34 +02:00
Miodrag Milanović e598b2f4d9
gatemate: special case RAMIO when needed (#1536) 2025-08-21 15:11:08 +02:00
Miodrag Milanović 82f8ff7cad
himbaechel: Extend API to enable cell delay override (#1535) 2025-08-20 06:32:18 +02:00
YRabbit 322ad920b3
Gowin. Enable GW5A series. (#1534) 
With the release of Apicula 0.22, the GW5A series gained support for
simple IO, LUTs (including Widw LUTs), and DFFs (including flip-flops 6
and 7 specific to the GW5A series), so we can include the GW5A-25A among
Gowin devices.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-15 07:12:09 +02:00
YRabbit 178021959c Gowin. Change the way DFF 6&7 presence is checked. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-14 12:33:48 +01:00
YRabbit 2d0ad9f9b1 Gowin. Use two additional DFFs. 
The GW-5A series has 8 flip-flops in a cell instead of 6. These
additional flip-flops can be used if the control network matches that
for the 4th and 5th DFFs in this cell.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-14 12:33:48 +01:00
Miodrag Milanović 95ab16f380
gatemate: add IOSEL as separate primitive (#1533) 2025-08-14 12:20:24 +02:00
Will MacCormack b0626280e9 Change Hash Embed check to check for erroneous signed #embed 2025-08-10 21:39:16 +01:00
Lofty 5355222e09 Revert "gatemate: don't place cells all at once (#1528)" 
This reverts commit 2d393c2487.
 2025-08-09 04:35:20 +01:00
Lofty 2d393c2487
gatemate: don't place cells all at once (#1528) 2025-08-08 18:19:42 +02:00
Lofty 0ad43e6ec7
gatemate: remove placement density restriction (#1527) 2025-08-08 17:02:56 +02:00
YRabbit 0be6173064 Gowin. Add pin configurations bel/cell. 
Prior to the 5A series, pin functions (GPIO/SSPI/JTAG/DONE/etc) were
switched using fuses. This was done during the binary image formation
stage for loading into the FPGA using the command line keys of the
gowin_pack program.

The 5A series features certain ports that connect to VCC or GND
depending on whether the pin is used as SSPI or GPIO, for example. This
mechanism exists in parallel with fuses, but it is not described
anywhere, nor is there a corresponding primitive.

To generate working images, we have no choice but to simulate this thing
at the nextpnr stage, since VCC/GND routing is required.

For now, two flags are added, responsible for the SSPI and I2C pin
functions.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-08 13:27:37 +01:00
YRabbit 8ce9918405 Gowin. Remove search for old Apicula. 
This item is likely no longer necessary, as this executable file has
been unavailable since May, with the complete transition to Himbaechel.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-06 00:32:41 +01:00
Lofty 8938c73fc9
Merge pull request #1524 from YosysHQ/lofty/gatemate-mult-router 
gatemate: multiplier router
 2025-08-05 11:20:25 +01:00
Miodrag Milanovic 6b11a82d04 cleanup 2025-08-04 14:28:43 +02:00
Miodrag Milanovic f0e03ed6e7 cleanup 2025-08-04 14:23:18 +02:00
Miodrag Milanovic 89e7e059d8 cleanup 2025-08-04 13:55:19 +02:00
Miodrag Milanovic eb77362b97 Added logs under debug, and removed include for idstring.h 2025-08-04 13:50:19 +02:00
Miodrag Milanovic 88f52bcaba Fix multipliers on hardware 2025-08-04 13:26:26 +02:00
Lofty 60f3c25cb0 refactor inversion checker 2025-08-02 15:23:56 +01:00
Lofty fe7546fda5 Multiplier routing needs priority over clocks 2025-08-02 14:00:25 +01:00
Miodrag Milanovic 0810a9a243 More multiplier fixes 2025-08-02 13:04:13 +02:00
Miodrag Milanovic 6a3c4a2dca Enable pack_mult 2025-08-01 17:47:07 +02:00
Miodrag Milanovic 1748f38aad Add MULT_INVERT property 2025-08-01 17:46:48 +02:00
Lofty d26fc19724 clangformat 2025-08-01 16:46:22 +01:00
Miodrag Milanovic 49001df290 Fix when width is 1 2025-08-01 14:46:54 +02:00
Miodrag Milanovic da5d42dc9d Add missing connection 2025-08-01 12:25:22 +02:00
Lofty d53f774078 re-disable multiplier packing 2025-07-31 14:54:43 +01:00
Lofty 341e288488 fix swapped B inputs 2025-07-31 14:50:36 +01:00
Miodrag Milanovic 7d8b7da20b Add missing connection 2025-07-29 14:01:07 +02:00
Miodrag Milanović 7e68bea863
gatemate: fix SER_CLK wiring from CLKIN to PLL (#1523) 
* gatemate: fix SER_CLK wiring from CLKIN to PLL

* fix some output formatting

---------

Co-authored-by: Patrick Urban <patrick.urban@web.de>
 2025-07-29 11:26:49 +02:00
Lofty d26aa342b7 bugfix for x2y2 in8 binding a pip twice 2025-07-29 09:37:45 +01:00
Lofty ac8a12aee5 bugfix for number of hops 2025-07-29 09:37:45 +01:00
Lofty ff9fa6f4cc route comments 2025-07-29 09:37:45 +01:00
Lofty 95b32a2b56 working diagonal router; unhappy inversion checker 2025-07-29 09:37:45 +01:00
Lofty 9837b6f676 current progress (broken diagonal router) 2025-07-29 09:37:45 +01:00
Lofty 80664e55b7 current progress (fixed routing done?) 2025-07-29 09:37:45 +01:00
Lofty 78b614ed31 current progress 2025-07-29 09:37:45 +01:00
Lofty 1576703937 current progress (route zero driver too) 2025-07-29 09:37:45 +01:00
Lofty d1f80ca5bb current progress 2025-07-29 09:37:45 +01:00
Lofty 4cf33090a9 current progress 2025-07-29 09:37:45 +01:00